Video line processor

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382 47, 382 41, G09G 100, G06K 936

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active

048191906

ABSTRACT:
A video line processor for varying the size of a video image portion along a video line in an image processor in which image size variation occurs first along horizontal lines and then along vertical lines and in which intermediate and final frames are stored in memories in which row and column addressing is interchanged on alternate frames. The line processor has a line memory for storing pixel values along each video line, has a pair of arithmetic circuits, one of which receives pixel values delayed in relation to pixel values received by the other, and has a coefficient memory with memory locations corresponding to pixel values along a video line, each of these locations being loaded between video frames with an address for the line memory and with coefficients for the arithmetic circuits to control, respectively, the position of each pixel value along a line and the transformation of the value.

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Woods et al., "Subband Coding of Images" 10/86 IEEE Trans. an ASSP vol. A-34 No. 5.

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