Video intermediate frequency signal processing circuit

Facsimile and static presentation processing – Facsimile – Specific signal processing circuitry

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358188, H04N 514

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active

051052733

ABSTRACT:
A video intermediate frequency signal processing circuit according to the present invention is so structured that a PLL state and a holding state are switched in response to a locking detection signal, a signal strength detection signal and a modulation factor detection signal. Thus, when it is set to enter the holding state at timing when the modulation factor of the video intermediate frequency signal is deep on the basis of the modulation factor detection signal, PLL output will not follow a video intermediate frequency signal at timing when the modulation factor is deep but follows only a video intermediate frequency signal at timing when the modulation factor is shallow, whereby correct video detection output can be regularly derived.
Further, the PLL state can be regularly attained regardless of the modulation factor of the video intermediate frequency signal in unlocking or in input of a weak electric field, on the basis of the locking detection signal and the signal strength detection signal, whereby responsibility similar to that in the prior art can also be secured.

REFERENCES:
patent: 4811096 (1989-03-01), Gakumura
P. Fockens, C. G. Eilers; Intercarrier Buzz Phenomena Analysis and Cures, IEEE Transactions on Consumer Electronics, vol. CE-27, No. 3, Aug. 1981, pp. 381-397.
A. Hamada, Phase-Lock Television IF Amplifier-Video Detector, IEEE Transactions on Consumer Electronics, vol. CE-21, No. 4, Nov. 1975, pp. 340-347.
M. Huber, H. Kriedt, R. Stepp, Modular Video IF Concept, IEEE Transactions on Consumer Electronics, vol. CE-29, No. 3, Aug. 1983, pp. 414-419.

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