Computer graphics processing and selective visual display system – Data responsive crt display control – Data responsive intensity control
Reexamination Certificate
1997-12-30
2001-02-20
Luu, Matthew (Department: 2779)
Computer graphics processing and selective visual display system
Data responsive crt display control
Data responsive intensity control
C348S673000
Reexamination Certificate
active
06191760
ABSTRACT:
FIELD OF THE INVENTION
The present invention relates to a video input level control circuit in a video appliance, more particularly to a video input level control circuit which can improve picture quality of the video appliance by selectively controlling input levels of the video signals inputted in different manners from the different-type video cards of a personal computer (PC).
BACKGROUND OF THE INVENTION
FIG. 1
shows the conventional video input level control circuit comprising a video input circuit
71
for amplifying a video signal inputted from a video card mounted on a PC
70
to a predetermined level; a video output amplifying section
73
for amplifying the video signal outputted from the video input circuit
71
to a predetermined output level, and outputting the amplified signal to a cathode ray tube (CRT)
72
; and a video input level control section
74
for controlling an input level of the video signal inputted from the video output amplifying section
73
to the CRT
72
.
The video output amplifying section
73
comprises a buffer transistor Q
1
for buffering the video signal inputted from the video input circuit
71
, and amplifying transistors Q
2
, Q
3
for cascode-amplifying the video signal outputted from the buffer transistor Q
1
.
A base terminal of the amplifying transistor Q
2
is connected to an emitter terminal of the buffer transistor Q
1
, and the emitter terminal of the amplifying transistor Q
2
is connected to the collector terminal of the amplifying transistor Q
3
. Bias voltages Vcc
1
, Vcc
3
are connected to the collector terminal of the transistors Q
1
, Q
2
via resistors R
1
, R
3
. A bias voltage Vcc
2
is connected to the base terminal of the amplifying transistor Q
2
, and CRT
72
is connected to the collector terminal of the amplifying transistor Q
3
. Resistors R
2
, R
4
are connected to the emitter terminal of the transistors Q
1
, Q
3
, respectively.
The video input level control section
74
comprises a detecting transistor Q
4
connected to the base terminal of the buffer transistor Q
1
via resistor R
5
for detecting abnormality of the video input level and switch-amplifying the detected video input level; a thermistor TH
1
connected to the base terminal of the detecting transistor Q
4
for detecting internal temperature of the product; a switching transistor Q
5
connected to the collector terminal of the detecting transistor Q
4
for controlling the emitter voltage level of the amplifying transistor Q
3
; and a transistor Q
6
connected to the collector terminal of the switching transistor Q
5
for controlling switching intervals of the switching transistor Q
5
.
The emitter terminal of the amplifying transistor Q
3
is connected to the collector terminal of the switching transistor Q
5
via the resistor R
4
, and the collector terminal of the transistor Q
6
is connected to the collector terminal of the detecting transistor Q
4
. A capacitor C
1
and a resistor R
11
are connected in parallel to the emitter terminal of the transistor Q
6
. A bias voltage Vcc
4
is connected to the collector terminal of the detecting transistor Q
4
via a resistor R
7
, and the bias voltage Vcc
4
is connected to the emitter terminal of the detecting transistor Q
4
via a resistor R
10
for setting a bias voltage level. A resistor R
13
is connected to the base terminal of the transistor Q
6
.
The transistors Q
1
-Q
4
and Q
6
are NPN-type transistors, and the transistor Q
5
is a PNP-type transistor.
The conventional video input level control circuit constituted above operates as follows.
If a video signal is inputted to the video input circuit
71
from the video card of the connected PC
70
, the video input circuit
71
amplifies the inputted video signal to a predetermined level. Then, the video input circuit
71
inputs the amplified video signal to the base terminal of the buffer transistor Q
1
of the video output amplifying section. Subsequently, the buffer transistor Q
1
buffers the inputted video signal and inputs the buffered video signal to the base terminal of the amplifying transistor Q
3
. The amplifying transistor Q
3
is then turned on, and the amplifying transistor Q
2
is subsequently turned on. The video signal is cascode-amplified by these two transistors Q
2
, Q
3
, and inputted to the CRT
72
. CRT
72
then displays an image according to the inputted video signal.
The video signal of the video input circuit
71
is also inputted to the base terminal of the detecting transistor Q
4
. Since the emitter standard voltage Ve of the detecting transistor Q
4
is set to be bias voltage Vcc
4
by the resistor R
10
, the base voltage Vb=0.7+Ve. Therefore, the detecting transistor Q
4
is turned on only at the voltage higher than the base voltage. In other words, if the video signal input level is applied to the CRT
72
as a normal voltage level, e.g., 0.7 V, the detecting transistor Q
4
is not turned on. Accordingly, neither the switching transistor Q
5
nor the transistor Q
6
is turned on, thereby never affecting the emitter voltage level of the amplifying transistor Q
3
.
However, if the video signal input level is applied to the CRT
72
at an abnormal level, e.g., high, or if an internal temperature of the product increases, the voltage level at the base terminal of the detecting transistor Q
4
becomes higher than Vb=0.7+Ve. In other words, if the internal temperature of the product affecting the video input level increases, the internal resistance of the thermistor TH
1
becomes greater, and consequently, the bias voltage Vcc
4
at the base terminal of the detecting transistor Q
4
becomes higher than Vb=0.7+Ve after passing through the thermistor TH
1
. In another case, if the video signal input level inputted through the video input circuit
71
is higher than the normal level, the video signal is applied to the base terminal at a voltage higher than the base voltage of the detecting transistor Q
4
. Accordingly, the detecting transistor Q
4
is turned on since the voltage level at the base terminal becomes higher than the standard voltage level Vb=0.7+Ve. The bias voltage Vcc
4
flowing to the base terminal of the switching transistor Q
5
subsequently changes its flow to the detecting transistor Q
4
. The switching transistor Q
5
is turned on as a consequence.
If the switching transistor Q
5
is turned on, the collector voltage level at the switching transistor Q
5
becomes higher, and the emitter voltage level at the collector terminal of the switching transistor Q
5
subsequently becomes higher. As a consequence, the amplification ability of the amplifying transistors Q
2
, Q
3
deteriorates, and the video input level applied to the CRT
72
can be automatically controlled.
If the switching transistor Q
5
is turned on, the transistor Q
6
is subsequently turned on, and controls operation of the detecting transistor Q
4
. As shown in
FIG. 2A
, the detecting transistor Q
4
recognizes the video signal which is as high as the base voltage as a starting signal, and operates imperfectly during the interval T
1
, as shown in FIG.
2
B. The transistor Q
6
is turned on only while the capacitor C
1
, which is discharged through the resistor R
11
having a great resistance value, is charged. While the transistor Q
6
is turned on, the voltage at the emitter of the detecting transistor Q
4
flows to the transistor Q
6
, thereby lowering the voltage level of the emitter of the detecting transistor Q
4
. Therefore, the detecting transistor Q
4
operates only while the transistor Q
6
is turned on. Thus, the turning-on interval of the detecting transistor Q
4
is determined by the interval of the capacitor C
1
. The interval of the capacitor C
1
is short as shown to be T
1
in FIG.
2
C. Accordingly, the video output level inputted to the CRT
72
rapidly becomes lower, and brightness of the screen can be controlled to be minimal.
The conventional video input level control circuit constituted above is thermally stable and can compensate the varied portion if the vid
Cha Eun A
Jun Il Jin
Blackman Anthony
LG Electronics Inc.
Luu Matthew
Oppenheimer Wolff & Donnelly
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