Television – Bandwidth reduction system – Format type
Patent
1994-05-11
1995-10-17
Kostak, Victor R.
Television
Bandwidth reduction system
Format type
348443, 348489, H04N 701
Patent
active
054595193
ABSTRACT:
A video image decoder architecture for implementing a processing algorithm in the 40-ms mode on high-resolution TV sets, of a kind adapted to handle TV signals being received on respective transmission channels (J,L), which comprises a video signal demultiplexer receiving the transmission channels (J,L); and respective processing blocks for separately handling the signals from each of the channels (J,L). Each processing block includes a video image format converter, a local memory connected to an output of the converter, and at least one median filter and one systolic filter cascade connected after the memory for restoring, by interpolation, signal samples related to successive lines of the video image. A summing node adds the outputs from each processing block so as to obtain a time mean between restored samples of the channels (J,L). This architecture drastically reduces the number of memories required for processing the restored algorithm, as well as reducing overall silicon area requirements for the system. Accordingly, the whole 40-millisecond processing portion may be integrated into a single chip.
REFERENCES:
patent: 4864398 (1989-09-01), Avis
patent: 5113242 (1992-05-01), Tsinberg et al.
patent: 5138448 (1992-08-01), Gillies et al.
patent: 5168358 (1992-12-01), Ishizu et al.
Poluzzi Rinaldo
Scalise Fabio
Kostak Victor R.
SCS Thompson Microelectronics, S.r.l.
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