Computer graphics processing and selective visual display system – Computer graphic processing system – Plural graphics processors
Patent
1994-07-21
1999-08-24
Mengistu, Amare
Computer graphics processing and selective visual display system
Computer graphic processing system
Plural graphics processors
345518, G09G 336
Patent
active
059430656
DESCRIPTION:
BRIEF SUMMARY
BACKGROUND OF THE INVENTION
This invention relates to a computer-based video/graphics memory system, namely method and apparatus.
As is well known, one form of computer memory is random access memory (RAM). This is in integrated circuit form, and may take the form of dynamic RAM or DRAM, or static RAM or SRAM. All types of RAM have a port through which random accesses to the memory locations may be made.
There is a need to use memory in a video/graphics or multi-processing applications. `Multi-media` is now becoming an important application of computer systems in which video signals at standard video line and field rates are intermixed for display with computer-generated graphics images. For display and for other purposes multiple sources and destinations of data need to have efficient and timely access to a common memory or storage device. It may be required to have simultaneous access to video, graphics and processed image data.
Conventional graphics sub-systems use dual-ported VRAM (video random access memory). The random access port is used by a host processor, or if present, a graphics processor, to create a graphics image by writing pixel values into a two-dimensional pixel array within the DRAM (dynamic RAM) core of the VRAM. A serial access port (SAM) is dedicated to reading out that data in raster line format, to refresh a cathode ray tube (CRT) display. The two ports, namely the normal random access port and the serial access port, function independently, except during transfers from the serial access port to DRAM core and vice versa.
There are problems in coordinating computer graphics and video signals in a single system. Our U.S. Pat. No. 5,027,212 describes one system for use in combining graphics and video information on a single display. Although extremely useful, there are limits on the capabilities of the system described in that patent.
SUMMARY OF THE INVENTION
The present invention in its various aspects is defined in the independent claims below, to which reference should now be made.
Various preferred embodiments are described below with reference to the drawings. In all these embodiments a memory device is provided with a random-access port for graphics data, a serial access port for output of data to a display, and an auxiliary port for video signal data. The data locations in the memory can selectively store both graphics data and video data. Thus video and graphics data can be overlaid on each other. Also, a video output can be made available additional to that through the serial access port. Finally data can be withdrawn through the auxiliary port, stored and/or processed and re-written back into memory, possibly at a different location.
The memory device can be a triple-ported semiconductor device, or can be dual or single ported memory provided with external multiplexing circuitry .
BRIEF DESCRIPTION OF THE DRAWINGS
Preferred embodiments of the invention will now be described in more detail by way of example with reference to the accompanying drawings, in which:
FIG. 1 is a block diagram of a conventional graphics display system illustrating the VRAM;
FIG. 2 is a similar diagram of a first graphics/video system in accordance with the present invention;
FIG. 3 is a block diagram illustrating a graphics accelerator which may be used in the system;
FIG. 4 is a block diagram illustrating the use of the system for multiple video displays and printing to a videotape;
FIG. 5 is a flow diagram illustrating a software solution to a problem with masked usage;
FIG. 6 is a block diagram illustrating components of a hardware solution to the same problem;
FIG. 7 is a block circuit diagram of a PC expansion card on which the system may be mounted;
FIG. 8 is a block diagram of a memory system in accordance with a second embodiment of the invention;
FIG. 9 illustrates the construction of the rate converting multiplier of FIG. 8;
FIG. 10 illustrates one possible construction for the control unit of FIG. 8;
FIG. 11 illustrates an alternative construction for the control unit of FIG. 8;
FIG
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Ashton Martin
Deacon Graham
Metcalfe John Anthony
Yassaie Hossein
Mengistu Amare
Videologic Limited
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