Video graphics memory storage reduction technique

Details Video graphics memory storage reduction technique Video graphics memory storage reduction technique

1988-05-02

1989-09-26

Shepperd, John W.

Facsimile and static presentation processing

Static presentation processing

Attribute control

358 21R, 358133, H04N 1104, H04N 713

Patent

active

048704792

ABSTRACT:
A video graphics memory storage reduction technique combines a frame buffer memory system with a run length encoded memory system by providing a luminance/chrominance decoder/multiplexer to convert output digital data segments from a memory into color components in lieu of using a color look up table. The digital data segments also are input to a detector and a switch, with the luminance portion being compared with a predetermined fixed value outside the valid luminance value range and the chrominance portion being passed through the switch in lieu of a constant when the luminance matches the detector value. A run length encoder logic circuit uses the output of the switch to generate access commands for the memory, and the detector causes the luminance/chrominance decoder to hold the last color until the next digital data segment is accessed by the logic circuit.

REFERENCES:
patent: 3860953 (1975-01-01), Cutler et al.
patent: 4125856 (1978-11-01), Netravali et al.
patent: 4479142 (1984-10-01), Buschman et al.
patent: 4541008 (1985-09-01), Fishman et al.
patent: 4731646 (1988-03-01), Kliem

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