Pulse or digital communications – Bandwidth reduction or expansion – Television or motion video signal
Reexamination Certificate
2001-08-27
2004-09-28
Vo, Tung T. (Department: 2613)
Pulse or digital communications
Bandwidth reduction or expansion
Television or motion video signal
Reexamination Certificate
active
06798833
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a video frame compression/decompression hardware system; and, more particularly, to a video frame compression/decompression hardware system for reducing an amount of memory.
2. Description of the Prior Art
In U.S. Pat. No. 5,838,597 to Pau et al, a method for reducing memory by optimizing an amount of the static memory required by an MPEG-2 decoder by using an adaptive differential pulse code modulation (ADPCM) technique is disclosed. The MPEG-2 video decoder (“video core” of the integrated system) accesses an external DRAM memory through an interfacing memory data bus, which can be also shared by an MPEG audio decoder core for accessing each audio buffer that may be organized in the same external DRAM. The video decoder may also include a controller for the management synchronisms.
According to a conventional MPEG-2 architecture, the decoder comprises a first-in-first-out (FIFO) buffer, for instance with a capacity of 1 Kbits for the acquisition and the writing of compressed data of the external DRAM, a start code detector, a memory bi-directional buffer for an on screen display (OSD) and a first variable length decoder for the compressed input data stream. The MPEG-2 discrete cosine transform (DCT) data decompression is carried out by the relative decompression units including a pipeline typically having a “run-length” decoding stage, an inverse quantization circuit, an inverse discrete cosine transform (I_DCT) processor and a network for the generation or construction of a predictor value.
In a known architecture, the blocks of I_DCT data output by the I_DCT processing circuit that calculates the inverse discrete cosine transform and the motion compensation, relative to the I, P and B pictures, were written in the respective buffers of the external memory in a coded form, that is, in the form of words of a certain number of bits before being decoded and sent to the display unit. By contrast, according to U.S. Pat. No. 5,838,597 to Pau et al, the decompressed I_DCT data relative to the I and P pictures are recompressed according to an ADPCM scheme before being coded and written in the respective buffer of the external memory. This is affected by means of an ADPCM coder. The recompressed data are thereafter decoded and decompressed by means of the ADPCM decoder in order to be sent to the display unit, together with decompressed B-pictures. Optionally, an internal auxiliary memory may be realized to optimize the management of the external memory as described hereinafter. In one preferred case of a “direct” reconstruction of the B-pictures, this is then realized as follows: the ADPCM compressed I and P predictors are read by the external DRAM memory and ADPCM decompressed in order to perform motion compensation of the B-picture that is currently being MPEG-2 decompressed by the pipeline.
FIG. 1
is a block diagram illustrating the recompression and the ADPCM encoder according to the cited U.S. Pat. No. 5,838,579 to Pau et al.
The ADPCM encoder comprises a 64*8 bit buffer (block buffer), a dedicated circuit (variance estimator), a ROM, a programmable logic array (PLA), a quantizer, a limiter circuit and a multiplexer.
The block buffer acquires the I_DCT input data and the variance estimator calculates the average pels value of each sub-block of the I_DCT input data and the average of the sum of the absolute values of the differences between each pel of the I_DCT data sub-block. Coefficients of quantization are stored in the ROM (non-volatile). The PLA receives, as an input, a certain variance value and outputs values of the required coefficients.
However, U.S. Pat. No. 5,838,579 to Pau et al does not disclose a hardware, which can pack seven codes having variable length into segments of fixed length and vice-versa. Also, 75% compression ratio is not disclosed, or a technique for simultaneously performing quantization. Additionally, Rice mapping is not mentioned so that optimization of an integrated circuit in the compression and decompression hardware cannot be achieved and it a takes long processing time.
FIG. 2
is a block diagram illustrating a quantization unit in a video frame compression and decompression hardware.
The quantization unit includes a first converting unit
210
, a quantizer
220
and a second converting unit
230
.
The first converting unit
210
includes a first sign reverser
213
and a multiplexer
211
. If frequency transformed coefficients are a positive sign (MSB is ‘0’), the coefficients are inputted in a positive part of the multiplexer
211
. If frequency transformed coefficients are a negative sign (MSB is ‘1’), the coefficients are inputted to the first sign reverser
213
and then the sign is reversed into a positive sign. The sign reversed coefficients are inputted into a negative part of the multiplexer
211
. The coefficients passed through the first converting unit
210
are inputted into the quantizer
220
and then quantized. The quantized coefficients have original signs as passing through the second converting unit
230
.
FIG. 3
is a diagram illustrating a Rice mapping unit in a video frame compression and decompression hardware.
The Rice mapping unit performs Rice mapping for the quantized coefficients. Two times operation, as performing 1-bit left shift, is performed for the qunatized coefficients and the positive reversion for qunatized coefficients originally having a negative sign is followed by subtraction of one, which is implemented by bit inverting. If the original sign of the Rice mapped coefficients before quantization is positive, the Rice mapped coefficients are inputted into a positive part of a multiplexer and if the original sign is negative, the Rice mapped coefficients are inputted into a negative part of the multiplexer.
SUMMARY OF THE INVENTION
It is, therefore, an object of the present invention to provide a video frame compression/decompression hardware system for reducing an amount of memory.
In accordance with an aspect of the present invention, there is provided a system performing compressing of a video frame, comprising: input control means for receiving and aligning data to be compressed; frequency transforming means for performing 1-dimensional and/or 2-dimensional frequency transformations of the data received from the input control; quantization and Rice mapping means for performing quantization and Rice mapping the transformed data outputted from the frequency transformation means; bit count combination means for calculating bit count for the quantized and Rice mapped data and for selecting one quantization value among the quantization values outputted from the quantization and Rice mapping means according to results of the bit count; encoding means for performing Golomb-Rice (GR) coding for the quantized and Rice mapped data and for packing the GR coded values, a DC value and the quantiztion value into a compression segment; and output control means for outputting the packed values.
In accordance with another aspect of the present invention, there is provided a system performing decompression of a video frame, comprising: input control means for receiving data to be decompressed; decoding means for unpacking the data and for performing Golomb-Rice (GR) decoding for the unpacked data; inverse Rice mapping and inverse quantization means for performing inverse Rice mapping for the GR decoded data and performing inverse quantization for the inverse Rice mapped data; inverse frequency transforming means for performing inverse 1-dimensional and/or 2-dimensional frequency transformation for the inverse Rice mapped and the inverse quantized data; and decompression output control means for outputting the desired pixels from the finally decompressed pixels obtained by the inverse frequency transformation.
In accordance with further aspects of the present invention, there is provided a system performing compression and decompression of a video frame, comprising: a compression system, including: input control means for receiving an
Jang Sung-Jae
Jeong Je-Chang
Kim Yong-Sik
Lee Tae-Young
Yoo Hoon
Hynix / Semiconductor Inc.
Jacobson & Holman PLLC
Vo Tung T.
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