Television – Format conversion
Reexamination Certificate
2000-01-19
2002-12-31
Kostak, Victor R. (Department: 2711)
Television
Format conversion
C348S581000
Reexamination Certificate
active
06501509
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a digital video processor and more particularly to an apparatus for converting resolution of an input digital image to a different resolution.
2. Discussion of Related Art
A digital TV receives images of various types and resolution (or picture quality) such as a high definition grade and a standard definition grade. Also, it is expected that there are provided various types of display devices in a digital TV, such as an existing cathode ray tube (CRT) TV or projection TV adapted to an interlaced scanning type, and a liquid crystal display (LCD) and plasma display panel (PDP) adapted to a sequential scanning type. Thus, a digital TV requires a format converter which converts the type and size of images in compliance with the format of the display device.
FIG. 1
is a block diagram of a general format converter, in which a plurality of format converters are used in parallel to convert various input formats to a desired output format.
In other words, if a format of an input image is 1080×1920 and a format of an output is also 1080×1920, the input image is output through a multiplexer
16
as it is. By contrast, if a format of an input image 720×1280, the input image is interpolated into 1080×1920 by a vertical 2:3 interpolation unit
11
and a horizontal interpolation unit
12
among a plurality of format converters in parallel connected with one another and then is output through the multiplexer
16
.
Also, if a format of an input image is 480×640 and a format of an output image is 1080×1920, the input image is interpolated into 1080×1920 by a vertical 4:9 interpolation unit
13
and a horizontal 3:8 interpolation unit
14
among a plurality of format converters in parallel connected with one another and then is output through the multiplexer
16
.
Likewise, if a format of an input image is 480×640 and a format of an output image is 1080×1920, the input image is interpolated into 1080×1920 by the vertical 4:9 interpolation unit
13
and a horizontal 1:3 interpolation unit
15
among a plurality of format converters in parallel connected with one another and then is output through the multiplexer
16
.
However, since a new format converter is required whenever a new input format is added, the size of hardware increases and correction of a circuit for a new input format or output format is not easy.
SUMMARY OF THE INVENTION
Accordingly, an object of the present invention is to solve at least the problems and disadvantages of the related art.
An object of the present invention is to provide a format converter for facilitating conversion of input/output formats by hardware.
Additional advantages, objects, and features of the invention will be set forth in part in the description which follows and in part will become apparent to those having ordinary skill in the art upon examination of the following or may be learned from practice of the invention. The objects and advantages of the invention may be realized and attained as particularly pointed out in the appended claims.
To achieve the objects and in accordance with the purposes of the invention, as embodied and broadly described herein, a format converter includes a memory unit for temporarily storing an input image, a delay unit for delaying data output from the memory unit for the unit of line or pixel, and an operation unit for calculating a weighted value a per clock and applying the weighted value &agr; to an output value of the memory unit and a delay value of the delay unit to obtain a new pixel value.
In a preferred embodiment of the present invention, the operation unit includes a calculating unit for calculating the weighted value &agr;, a multiplier for multiplying a difference value between a pixel value delayed by the delay unit and a pixel value input through the memory unit by the weighted value &agr;, and an adder for adding a pixel value from the delay unit to an output value of the multiplier. The calculating unit includes an adder for adding the number of input pixels to a feedback value, a modulo operation unit for allowing an output value of the adder to be feedback to the adder and also outputting a load signal to the memory unit and the delay unit so that a new data is loaded into them if the output value of the adder is greater than the number of output pixels, and at the same time for outputting the remainder divided the output value of the adder by the number of output pixels to the adder, and a divider for performing division using the output value of the modulo operation unit as a numerator value and the number of output pixels as a denominator value and for outputting the resultant value as a weighted value &agr;.
Furthermore, the calculating unit includes an initial value generator for generating an initial value required for format conversion using information on scanning types, information on color coordinate sampling, and information on the number of input pixels and the number of output pixels, an addend generator for generating addend using information on scanning types, information on color coordinate sampling, and information on the number of input pixels, an adder for initially outputting a value generated by the initial value generator and then adding addend generated by the addend generator to a feedback value, a modulo operation unit for outputting an output value to the adder and also outputting a load signal to the memory unit and the delay unit so that a new data is loaded into them if the output value of the adder is greater than the number of output pixels, and at the same time for outputting the remainder divided the output value of the adder by the number of output pixels to the adder, and a divisor calculator for calculating a denominator value required for division using information scanning types, information on color coordinate sampling, and information on the number of output pixels, and a divider for performing division using the output value of the modulo operation unit as a numerator value and the output value of the divisor calculator as a denominator value and for outputting the resultant value as a weighted value &agr;.
It is to be understood that both the foregoing general description and the following detailed description are exemplary and explanatory and are intended to provide further explanation of the invention as claimed.
REFERENCES:
patent: 5784114 (1998-07-01), Borer et al.
patent: 5838385 (1998-11-01), Reder et al.
patent: 6069670 (2000-05-01), Borer
Kostak Victor R.
LG Electronics Inc.
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