Computer graphics processing and selective visual display system – Computer graphic processing system – Graphic command processing
Reexamination Certificate
2000-05-05
2003-08-26
Bella, Matthew C. (Department: 2676)
Computer graphics processing and selective visual display system
Computer graphic processing system
Graphic command processing
C345S501000, C345S215000, C345S215000
Reexamination Certificate
active
06611269
ABSTRACT:
FIELD OF THE INVENTION
This invention relates to a video display unit including a set top box for receiving digital broadcasting signals which multiplex digital data such as compressed video signals or program information and for decoding and outputting the selected video signals. This invention also relates to a program recording medium.
BACKGROUND OF TECHNOLOGY
In accordance with the recent development of the digital technology, digital broadcasting services have been realized which use videos, audio, and data signals for broadcasting as digital signals in a unified way, and broadcast them by utilizing a satellite or the like.
In those services to provide tens or hundreds of channels of broadcasting by means of a compression multiplex technology represented by MPEG2 (standardized with ISO/IEC-13818) or the like. Each broadcasting service provider intends to complete a variety of services for implementing high definition video broadcasting and for realizing the differentiation such as an information service using still picture or the like by utilizing the characteristics of the digital broadcasting where all the signals for videos, audio, and data or the like are handled as digital signals, and a video display unit is required to cope with those.
An example of a conventional MPEG video decoder system is shown in
FIG. 14
, which will be described in operation in the following.
In
FIG. 14
, the numeral
100
denotes a system control means for controlling the entire system, the numeral
101
denotes a video decoding means for decoding MPEG, the numeral
102
denotes a frame memory for storing display data, and the video decoding means
101
stores video data to be decoded and graphics data of on-screen display (hereinafter referred to as OSD). The numeral
103
denotes a display timing generation means for generating a synchronizing signal or the like, the numeral
104
is a memory control means for controlling reading or writing of the frame memory
102
. The numeral
105
denotes an output buffer means for temporarily storing the display data read by the memory control means
104
. The numeral
800
denotes a video processing unit for generating display data by using the data of the output buffer means
105
, and the numeral
801
denotes a control timing generation means for controlling the video processing unit
800
.
FIG. 15
illustrates an exemplary internal configuration of the video processing unit
800
in the above mentioned MPEG video decoder system. The numerals
8001
and
8002
denote horizontal filter circuits for horizontal up/down scaling operations of the video data, the numeral
8003
denotes a vertical filter circuit for up/down scaling in the vertical direction the sequential two line data from the horizontal filters
8001
and
8002
, and the numeral
8004
denotes a blending circuit for switching between video data from the vertical filter circuit
8003
and the OSD data.
FIG.
16
(
a
) shows a video output format to be implemented at a receiver for digital broadcasting established by the DVB (Digital Video Broadcasting DOCUMENT A001-revision 1) standard.
In order to implement the horizontal and vertical up-scaling processing shown in FIG.
16
(
a
), the horizontal filter circuit
8001
and
8002
as well as the vertical filter circuit
8003
are provided with circuits in advance corresponding to the following magnifications.
horizontal filter circuits: 3/4, 1, 9/8, 4/3, 3/2, 2, 8/3
vertical filter circuits: 1, 2
FIG.
16
(
b
) shows a pan-scanning process, which cuts out and expands horizontally the central display portion (Pan & Scan Window) in case an input video with an aspect ratio 16:9 is outputted on a monitor with 4:3.
In this way, in a video display unit for a digital broadcasting receiver, the horizontal and vertical up-scaling processing of the video signals has become an indispensable function.
The MPEG decoder system in
FIG. 14
is described in operation in the following.
The system control means
100
inputs a bit stream corresponding to a channel the user has selected into the video decoding means
101
.
The video decoding means
101
picks out information for the input resolution of FIG.
16
(
a
) in the bit stream to be transferred to the system control means
100
. The video decoding means
101
performs the MPEG video decode processing by using the frame memory
102
as a reference frame buffer and a display frame buffer. A description for the MPEG decode processing is omitted in the detailed operation, since it doesn't directly relates to the purpose of the present invention.
The system control means
100
draws the on-screen display (OSD) data for the frame memory
102
in parallel with the decode control. This is program table data called operational information of the menu or the like or the EPG (Electronic Program Guide). In the video display, the system control means
100
controls the memory control means
104
to read out the video data decoded from the frame memory
102
and the OSD data per line unit. The data read out per line unit is temporarily stored in the output buffer means
105
.
The system control means
100
, in compliance with the resolution information of the input video picked out of the video decoding means
101
and the aspect ratio of the output monitor indicated in advance by the user, sets the up-scaled ratio of the horizontal filter circuits
8001
and
8002
as well as the vertical filter circuit
8003
in the video processing unit
800
so as to control the up-scaling processing shown in the FIG.
16
(
a
). The decode video processed for up-scaling is outputted externally after blended with the OSD data at the blending circuit
8004
.
In this way, the conventional video processing unit in the MPEG decoder system is provided with a dedicated circuit corresponding to the up-scaled ratio set in advance and a blending circuit with the OSD data, to generate a display output complying to the resolution information or the like of the decode video.
FIG. 17
shows a block diagram of the MPEG decoder system for implementing a still picture display in addition to an video and an OSD displays in order to correspond to a still picture information service. The video processing unit
800
is provided with two system horizontal filter circuits
8001
and
8002
as well as a vertical filter circuit
8003
to control for video data and still picture data respectively and is further provided with a blending circuit (
1
)
8005
for switching between the video data and the still picture data.
In operation, the system control means
100
draws not only the OSD data but also the still picture data for the frame memory
102
. The still picture data are sent by utilizing data broadcasting such as digital satellite broadcasting, or are sent through the telephone line. In any case, the data are obtained by the operation of the user and displayed by the control of the system control means
100
. The still picture data written in the frame memory
102
are read out to the output buffer means
105
per line unit together with the video data and the OSD data by the memory control means
104
. At this time, in case the vertical filter processing is performed for the video data, sequential two lines of data are read out for the video data.
Using those data, down-scaling processing is carried out independently for the video and the still picture data by the video processing unit
800
shown in
FIG. 17
, and by blending the result of this operation with the OSD data, an output video as shown in
FIG. 17
can be gained.
As described above, the conventional video display unit is implemented by having a dedicated circuit as shown in
FIGS. 15 and 17
corresponding to a different display specification depending on each service provider. Those are usually built in as part of the MPEG video decoder LSI circuit.
On the other hand, the digital broadcasting standards for the ground wave in the U.S.A. correspond to as much as high definition system with three kinds of numbers of scanning lines
1080
,
720
and
480
and with two kinds of s
Goto Shoichi
Kurita Naoki
Uehara Hirotoshi
Bella Matthew C.
Matsushita Electric - Industrial Co., Ltd.
Monestime Mackly
Smith , Gambrell & Russell, LLP
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