Computer graphics processing and selective visual display system – Display peripheral interface input device – Light pen for fluid matrix display panel
Reexamination Certificate
1997-12-08
2001-06-05
Hjerpe, Richard (Department: 2674)
Computer graphics processing and selective visual display system
Display peripheral interface input device
Light pen for fluid matrix display panel
C345S060000, C345S063000, C345S213000
Reexamination Certificate
active
06243073
ABSTRACT:
FIELD OF THE INVENTION
The present invention relates to video display monitors including plasma displays which employ a subfield method for overlapping weighted multiple binary video screens in a time base for display.
BACKGROUND OF THE INVENTION
The use of plasma display monitors has recently expanded into the area of color display monitors which offer drastically slimmer units. Plasma display monitors employ a subfield method for displaying half tone, as disclosed in Japanese Laid-open Patent No. H4-195087. In DC plasma display monitors, for example, their driving method may require display data write and sustaining periods as disclosed in Japanese Laid-open Patent No. H6-12988. Configuration of a video display monitor of the prior art is explained next with reference to
FIGS. 15
,
16
, and
17
.
FIG. 15
shows the configuration of a video display monitor of the prior art employing a single scanning system driving method. The conventional video display monitor comprises a synchronizing signal separator
1
for separating the video signal, a timing pulse generator
2
for producing a timing pulse in accordance with the synchronizing signal separated by the synchronizing signal separator
1
, an A/D converter
3
for converting the video signal to digital signal, a subfield processor
4
, a frame memory
5
required for the subfield processor
4
, a DC plasma display panel
9
, an anode driving circuit
6
for the DC plasma display panel
9
, a cathode driving circuit
7
, and an auxiliary anode driving circuit
8
.
In the video display monitor as configured above, the A/D converter
3
converts the video signal to a digital signal, and outputs the digital signal to the subfield processor
4
. At the same time, the synchronizing signal separator
1
separates the synchronizing signal from the video signal. The timing generator
2
produces a timing pulse required in the subfield processor
4
and A/D converter
3
in accordance with the synchronizing signal output from the synchronizing signal separator
1
. The subfield processor
4
implements the following operations with the frame memory
5
.
The subfield processor
4
divides one field of the video signal into multiple subfields in order to display grey levels of the video signal, and outputs a required signal to the cathode driving circuit
7
and auxiliary anode driving circuit
8
. The subfield processor
4
also converts the input video digital signal for obtaining grey levels of the video signal using the subfield method, and supplies the converted signal to the anode driving circuit
6
. A group of anode electrodes is connected in the vertical direction of the screen to each of the multiple anode electrode terminals. Similarly, a group of auxiliary anode electrodes is connected in the vertical direction of the screen to each of multiple auxiliary anode electrode terminals. A group of cathode electrodes is connected in the horizontal direction of the screen to each of the multiple cathode electrode terminals. A line created by connecting these cathode electrodes horizontally is called a scanning line hereafter.
FIGS. 16A
to
16
E show waveforms of driving circuits of a plasma display panel
9
. These figures explain the relation between a signal (pulse) applied to the anode electrode terminal and signals applied to the cathode terminal and auxiliary anode electrode terminal, using one anode electrode terminal.
First, the cathode driving circuit
7
outputs an “active low” write pulse SC from a first cathode electrode terminal K
1
(hereafter referred to as the “scanning line K
1
.”) to a last cathode electrode terminal Km as shown in
FIGS. 16C
to
16
E. Referring to
FIG. 16B
, the anode driving circuit
6
outputs a synchronized “active high” write pulse, and video data DK
1
, DK
2
, DK
3
, etc. which corresponds to each scanning line of the anode electrode terminal. Similarly, the auxiliary anode driving circuit
8
outputs an “active high” auxiliary anode pulse synchronized to the write pulse, for priming discharge, to the auxiliary anode electrode terminal as shown in FIG.
16
A. The auxiliary anode pulse is output to assure discharge in the anode electrode.
As explained above, the write pulse is successively applied from the scanning line K
1
to Km. At the same time, video data corresponding to each cathode of each scanning line is applied to each successive anode electrode terminal, and the auxiliary anode pulse is applied to the auxiliary anode electrode terminal.
Referring to
FIG. 16E
, the cathode driving circuit
7
then outputs a sustaining pulse during a sustaining period (SUS) after the output of the write pulse. The sustaining pulse is applied to assure discharge in the anode electrode terminal for securely illuminating the plasma display panel. The length of the sustaining period corresponds to the weight of the digital video signal.
FIG. 17
shows an example of the subfield method which repeats write and sustaining operations for displaying the video image in an 8-bit 256 grey-level. In
FIG. 17
, time is plotted along the abscissa, and the scanning lines K
1
to Km are plotted along the ordinate. In this case, a driving period Tk
0
in one-field period Tf
0
is divided into eight subfields SF
1
to SF
8
. In this example, the length of the sustaining period in a first subfield SF
1
corresponds to the MSB (Most Significant Bit), that is 128t (where t is a predetermined unit of period). In other words, the same length of the sustaining period is given to each scanning line from K
1
to Km in the same subfield.
After completing the scanning of the first subfield, a second subfield SF
2
is scanned. In the second subfield, the anode driving circuit
6
outputs video data to the anode electrode terminal. This video data corresponds to the second significant bit (2nd SB) in the digital video signal of each scanning line. The cathode driving circuit
7
outputs the sustaining pulse to each scanning line during the sustaining period corresponding to the second significant bit (2nd SB) after the write pulse. The length of the sustaining period for the second subfield, that is the second significant bit, is 64t for example. Likewise, the anode driving circuit
6
outputs video data, corresponding to each bit in the digital video signal of each scanning line, to the anode electrode terminal in each subfield. The length of the sustaining period for the third subfield SF
3
, that is the third significant bit, is 32t for example. For each subfield, the length of the sustaining pulse is set to correspond to the bit weight. In an eighth subfield SF
8
, the length of the sustaining period is 1t for example.
Accordingly, the conventional video display monitor is capable of displaying a video image in 256 grey-levels by controlling the illumination sustaining period for each pixel to correspond to each digital signal value.
In the above explanation, the conventional video display monitor employs a single scanning system as the driving method. On the other hand, there are video display monitors which employ the double scanning system as the driving method. In the driving method employing the double scanning system, electrodes of the plasma display panel are divided into two groups: an upper group and a lower group. These groups are controlled independently and simultaneously for displaying video images by dividing one field into nine subfields or more. A video display monitor employing the double scanning system is explained next with reference to
FIGS. 18
,
19
, and
20
.
FIG. 18
shows the configuration of a video display monitor of the prior art employing the double scanning system. The conventional video display monitor comprises a synchronizing signal separator
1
for separating the video signal, a timing pulse generator
2
for producing a timing pulse in accordance with the synchronizing signal separated by the synchronizing signal separator
1
, an A/D converter for converting the video signal to digital signal, a subfield processor
4
, a frame memory
5
required for the subfield processor
4
, a D
Hirano Takehisa
Kasahara Mitsuhiro
Kawamura Hideaki
Nakai Katsuhiro
Ohira Kazuo
Hjerpe Richard
Matsushita Electric - Industrial Co., Ltd.
Nguyen Frances
Ratner & Prestia
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