Computer graphics processing and selective visual display system – Plural display systems – Tiling or modular adjacent displays
Reexamination Certificate
1999-03-26
2002-11-05
Saras, Steven (Department: 2675)
Computer graphics processing and selective visual display system
Plural display systems
Tiling or modular adjacent displays
C345S083000
Reexamination Certificate
active
06476779
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a video display device suitable for application to a large video display device or the like. Specifically, the present invention relates to a video display device capable of performing a high-speed switching process and displaying an image without video flicker, wherein a memory means is provided for dots, which are arranged over p rows and q columns to form each individual unit cell of a display part, and wherein the memory means stores video data to be supplied to display elements constituting the dot, in a one-frame unit or a one-field unit, and wherein the video data may be displayed while dot groups are switched alternatively at high speed in the same frame or field.
2. Description of the Related Art
A large video display device has been set up in a place for doing various events outdoors, outdoor or indoor stadium, sport facilities, and so forth. The large video display device displays the contents of events, the results of competition, and so forth on a large-sized video display part such as a panel or a screen, thereof.
The video display device
10
for this purpose has a video source (e.g., a VTR or the like)
12
, as shown in FIG.
1
. The video source
12
transmits video sources (the contents of events, the contents of competition, drama programs, and so forth) to a signal processing device
30
where they are converted into a signal form suitable for a video display part
14
. Thereafter, the signal processing device
30
transmits the converted signal to the video display part
14
and then a desired image or picture is displayed on the video display part
14
. The video display part
14
is constructed so as to be suitable for a large screen (e.g., 4 m×3 m).
The video display part
14
is a collection of a plurality of dots.
FIGS. 2A through 2C
show an example thereof. In the example, a unit dot (hereinafter called “dot”)
16
comprises a trio of display elements, each of which emits light of red R, green G or blue B, as shown in FIG.
2
A. The dots
16
are arranged over p rows and q columns (both p and q are four in the illustrated example) to form each individual unit cell
18
(see FIG.
2
B). Further, the unit cells are arranged over m rows and n columns (both m and n are four in the illustrated example) to form a display unit
20
as a unit (see FIG.
2
C). A large video display part
14
is constructed by a collection of the display units
20
.
In such a video display part
14
, separate drivers drive respectively the display elements themselves defined as an RGB trio constituting the dot
16
in order to obtain sufficient luminous brightness, for example. The unit cell
18
is normally formed by 16 dots (4×4 dots) and thus forty-eight individual drivers drive forty-eight display elements (16 dots×3 elements).
Even if each unit cell is represented as 4×4=16 dots as shown in
FIG. 3
, forty-eight drivers corresponding to forty-eight display elements cause a drive circuit to increase in size. As means for solving this, means for reducing the number of drivers to ½ by providing switching or selector means such that one driver drives two display elements has been proposed.
FIG. 4
is a fragmentary systematic diagram showing one example of the proposal. When one unit cell consists of forty-eight display elements as shown in
FIG. 3
, a driver circuit
32
is constructed so as to drive twenty-four display elements corresponding to ½ of the forty-eight display elements. Thus, the driver circuit (IC driver)
32
comprises latch circuits
33
a
through
33
x
for latching twenty-four video data S
0
through S
23
and drivers
34
a
through
34
x
electrically connected to the latch circuits at their subsequent stages as shown in FIG.
4
. Each of the respective drivers
34
a
through
34
x
is connected to their corresponding display elements RU
0
through BL
7
via switching means
35
and then the driver circuit
32
transmits the outputs of drivers
34
a
through
34
x
to the display elements RU
0
through BL
7
.
In the unit cell as shown in
FIG. 3
, eight dots of an n row and an n+2 row (upper-stage dot group U) are simultaneously driven. Next, eight dots of the remaining n+1 row and n+3 row (lower-stage dot group L) are also simultaneously driven. That is, these dot groups, i.e., display element groups U and L are alternately driven in a predetermined cycle. Here, each set of the display elements RU
0
through RU
7
, GU
0
through GU
7
and BU
0
through BU
7
emits respectively the same light-emitting color. Similarly, each set of the display elements RL
0
through RL
7
, GL
0
through GL
7
and BL
0
through BL
7
emits respectively the same light-emitting color.
An example of the alternate driving of the dot groups U and L will be shown in
FIGS. 5A through 5C
. These figures show the case in which they are alternately switched over plural times (about sixteen times) at time intervals (each corresponding to {fraction (1/30)} second) of individual one frame. During this period of time for one frame, the same video data is supplied to the corresponding display element group.
On the other hand, when these upper and lower dot groups U and L are alternately shifted, the video data is latched at the timing as show in FIG.
5
B and the latched video data is supplied to the display elements comprised of a first dot group (upper dot group) U corresponding thereto in a cycle. Then, in the next cycle, the video data is also latched at the timing as shown in FIG.
5
C and the latched video data is supplied to the display elements comprised of a second dot group (i.e., a lower dot group) L. Such latching operations must be repeated ten-odd times during every one frame. Namely, a high-speed latching is necessary therefor.
Actually, however, it is very difficult to drive the display elements while latching the video signal at high speed as described above. Further, it is necessary to use a high-speed element to implement the high-speed latching. This causes the cost of the entire video display device to rise. Further, using the low-speed latching causes an occurrence of the video flicker.
With the foregoing problems in view, it is therefore an object of the present invention to provide a video display device capable of performing the high-speed switching processes and preventing the video flicker from occurring.
SUMMARY OF THE INVENTION
According to one aspect of this invention, for achieving the above object, there is provided a video display device comprising a display unit including a unit cell, the unit cell comprising a plurality of dots arranged vertically and horizontally relative to each other, each dot being comprised of a plurality of display elements. In the video display device, the dots are divided into a plurality of dot groups and the dot groups are switched alternatively and successively. Further, the video data corresponding to the dot groups is read from the memory means storing the same. Then, a driving means drives display elements in the dot groups based on the read video data.
Further, a plurality of the memory means repeat the read and write operations of video data to be supplied to the display elements in one-frame or a one-field unit. The memory means are switched successively every one frame or one field.
According to this invention, the dot groups comprise a plurality of dot groups and then the dot groups are alternately switched. Display elements of the dot are driven. Further, since the data stored in the memory means is simply read out as the video data in this case, it allows the read time of the video data to become short even when a switching cycle is repeated at a high speed.
Further, in this invention, there is provided a plurality of memory means for storing video data in one-frame unit, or a one-field unit. The video data of one frame are written to one of the memory means using an immediately preceding frame period. During the period when the driving means reads the video data from t
Okamoto Eizo
Yano Motoyasu
Anyaso Uchendu O.
Saras Steven
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