Video display and decode utilizing off-chip processor and DRAM

Details Video display and decode utilizing off-chip processor and DRAM Video display and decode utilizing off-chip processor and DRAM

2003-12-02

2011-12-13

Liu, Shuwang (Department: 2611)

Pulse or digital communications

Bandwidth reduction or expansion

Television or motion video signal

C375S240020, C375S240260, C375S240000, C375S250000

Reexamination Certificate

active

08077778

ABSTRACT:
A system, method, and apparatus for decoding and displaying images utilizing two processors and two memory units. The decode process receives images which are encoded according to a predetermined standard. Included with the encoded images are parameters which facilitate the decode and display processes. The decode process decodes the encoded images and the encoded parameters and stores each image in a separate image buffer, and each set of associated parameters in a buffer descriptor structure associated with the image buffer. The decode process is carried on by the first processor. The display process utilizes the parameters associated with the image to determine the appropriate display order for each image, and then display the image accordingly on a display device, based on the associated parameters. The first processor carries on the display of the image on the display device. The second processor determines the display order for the images. The second processor and the second memory can be off-chip.

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