Video decoding system

Details Video decoding system Video decoding system

1999-02-01

2003-02-25

Rao, Andy (Department: 2613)

Television

Image signal processing circuitry specific to television

With details of static storage device

C375S240230

Reexamination Certificate

active

06525783

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a high definition television (HDTV) video decoder and more particularly to a video decoding system for decoding bit streams of motion picture experts group 2 main profile at high level (MPEG2 MP@HL).
2. Description of Related Art
Recently, digital TV broadcasting has attracted a great among of attention. Accordingly, extensive research for compression and transmission of digital video data have been made to provide distinct pictures of high definition through television receivers at home. As a result, a MPEG2 has been developed which is mainly used as an algorithm for compressing video signals.
Even with the existing technology, transmitting digital data of high quality video had been difficult due to it's high data rate. Because the MPEG2 allows a very high compression rate, for example 1/40 to 1/60, utilizing the MPEG2 algorithm, research has been made to transmit digital data of high definition to TV receivers at home via general broadcasting channels. However, to view the digital data, a digital TV receiver requires a video decoder to reconstruct the original high definition video data from the received compressed data. Particularly, the speed necessary in the decoder to decode the high definition video signals is five or six times the speed of a usual video decoder. Also, greater amount of memory capacity is required to decode. the high definition video signals.
FIG. 1
is a block diagram of a conventional video decoder for processing video signals having a normal resolution in which the compressed video data is transmitted at a rate of 15 MBytes per second.
When a zig-zag scan coded video bit stream is serially input to the decoder, it is variable length decoded at a variable length decoder (VLD)
11
and separated into motion vectors, a quantization value, and discrete cosine transform (DCT) coefficients. Through an inverse scanner (IS)
12
and an inverse quantizer (IQ)
13
, a value of the DCT coefficients output from the VLD
11
is transmitted to an inverse discrete cosine transform (IDCT) unit
14
.
The DCT coefficients are decoded into a run/level form at the VLD
11
. Namely, a DCT block comprises of 8 by 8 non-zero coefficients such that the output of the VLD
11
is the level data indicating the amplitude of the non-zero coefficients and the run data indicating the number of zeros inserted between the coefficients. The run/level pairs are sequentially converted into 64 DCT coefficients through a run/level decoding and output to the IS
12
. In order to improve efficiency of the run/level code, the 8 by 8 coefficients are decoded in the form of zig-zag scanning in which low frequency elements are primarily transmitted. Because the 8 by 8 coefficients decoded in such form, the IS
12
converts the zig-zag scan into a raster scan.
The IQ
13
dequantizes the inverse scanned 64 DCT coefficients according to the quantization value and outputs the dequantized data to the IDCT unit
14
. The IDCT unit
14
performs the IDCT with respect to the dequantized DCT coefficients and outputs the IDCT coefficients to a motion compensation unit
15
. The motion compensation unit
15
combines the, data compensated by the motion vectors from the VLD
11
with the IDCT data to reconstruct the original image and outputs the reconstructed image to a display unit
16
. After rearranging the data according to a picture type if necessary, the display unit
16
outputs received data for viewing.
During the decoding process., an external memory, for example, a dynamic RAM (DRAM)
22
, is utilized as the frame memory. The DRAM
22
is generally divided into reading and writing of a bit stream for variable length decoding, reading of data necessary for the motion compensation, and writing and reading decoded video data to be displayed. Also, the VLD
11
, MC
15
, and display unit
16
has at least one first input first output (FIFO)
17
~
20
for temporarily storing data to prevent data collision on a bus, and for transmitting and receiving data through a memory controller
21
.
A single memory may be utilized for multiple functions if a plurality of memory access requests can be managed and processed. Because the request signals of each block to access the memory access are necessary for the video decoding, the signals must be well controlled to enhance the decoding efficiency. To control the signals, the memory controller
21
divides the access time for performing each function, usually with respect to a macroblock.
Moreover, the bit streams are not uniformly compressed by one specified method, but are compressed according to the characteristics of the corresponding macroblocks. However, the volume of data to be processed is different at for each block and unnecessary memory access may be allocated by assigning a fixed access time, resulting in a deterioration of efficiency. Additionally, the conventional video decoder shown in
FIG. 1
may be appropriate for processing a small amount of data, but its processing speed is insufficient for processing data of a HDTV decoder which involves processing a great amount of data.
Particularly, the decoding of MPEG2 MP@HL video data involves an amount of data approximately 6 times greater than the amount involved in the decoding of normal resolution video data. Thus, the data must be processed at a rate of more than 93 Mbytes per second. Accordingly, a HDTV decoder must process data at a speed 6 times faster than the conventional video decoder as shown in
FIG. 1
, and the memory capacity and data transmission speed must also be increased proportionately to the increased speed.
Most of the DCT coefficients in a compressed bit stream are 0, allowing the VLD
11
to decode one block within 5 to 6 clocks. However, a run/level decoder generate the 64 DCT coefficients by inserting zeros in the appropriate places and requires 64 clocks. As a result, the VLD
11
mostly remains idle while the run/level decoder generates the DCT coefficients, thereby creating an inefficiency.
If a conventional video decoder implemented to process the HDTV video data, the VLD, run/level decoder, inverse scanner, and IQ must operate at a maximum clock of 94 MHz. However, this clock frequency too high and decoding cannot be performed without undue burden on the hardware. Moreover, the inverse scanning is serially performed, requiring the internal memory writing and reading to perform at very high speed.
SUMMARY OF THE INVENTION
Accordingly, an object-of the present invention is to solve at least the problems and disadvantages of the related art.
An object of the present invention is to provide a video decoding system which allows a parallel processing when high speed is required and/or a serial processing when high speed is not required.
Another object of the present invention is to increase the memory access speed in a video decoding system by utilizing a synchronous DRAM (SDRAM) as a frame memory and by effectively managing the memory requests from different system blocks.
A further object of the present invention is to provide a video decoding system which minimizes the necessary time for memory access for motion compensation.
Additional advantages, objects, and features of the invention will be set forth in part in the description which follows and in part will become apparent to those having ordinary skill in the art upon examination of the following or may be learned from practice of the invention. The objects and advantages of the invention may be realized and attained as particularly pointed out in the appended claims.
To achieve the objects and in accordance with the purposes of the invention, as embodied and broadly described herein, a video decoding system according to the present invention generally includes a VLD, an IQ, an IS, an IDCT unit, a motion compensation unit, a half pel prediction unit, and a memory controller, allowing control of the processing time depending upon a video bit stream compression method.


REFERENCES:
patent: 5963222 (1999-10-01)

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