Video decoder with parallel implementation

Details Video decoder with parallel implementation Video decoder with parallel implementation

1993-09-30

1994-10-18

Kostak, Victor R.

Television

Bandwidth reduction system

Data rate reduction

348407, H04N 713

Patent

active

053572823

ABSTRACT:
An image decoder for discrete cosine transform and motion compensation which separately performs a process for inverse quantization and inverse discrete cosine transform in the unit of 8.times.8 block and a process for motion compensation in the unit of 16.times.16 block and processes an image frame to be motion compensated by dividing the image frame into four phases and then compensates for the scanning difference between the respective processed video signals so as to be matched with each other. According to the present invention, real time processing of video signal with low speed clock frequency and stable motion compensation in the contour portion of subpictures are enabled, thereby improving picture quality.

REFERENCES:
patent: 4717956 (1988-01-01), Moorhead et al.
patent: 4953023 (1990-08-01), Kondo
patent: 5012337 (1991-04-01), Gillard
patent: 5132792 (1992-07-01), Yonemitsu et al.
patent: 5134477 (1992-07-01), Knauer et al.
patent: 5144423 (1992-05-01), Knauer et al.
patent: 5157742 (1992-10-01), Niihara

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