Video decoder having asynchronous operation with respect to a vi

Television – Bandwidth reduction system – Data rate reduction

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348384, H04N 732

Patent

active

054537908

ABSTRACT:
A video decoder is proposed which receives packets of video information relating to moving video images from a packet switching network. The video decoder provides for the elimination of a great deal of hardware overhead and also provides for increased flexibility compared to prior art decoders by letting the decoding process, implemented via a decoder (DEC1, DEC2), run asynchronously with respect to the display process, implemented via a display (DIS). Moreover, and also in contrast with prior art decoders, the video decoder is not explicitly synchronized to its corresponding encoder by explicitly recovering the system clock of the encoder. This is realized through buffering actions within a frame store memory (FSM) placed between the decoder (DEC1, DEC2) and the display (DIS). The variable length of such a buffer can be used to control the speed of the display process in order to prevent underflow or overflow of the latter buffer and corresponding image degradation. The latter is done via a control device (CON).

REFERENCES:
patent: 5185819 (1993-02-01), Ng et al.
patent: 5227882 (1993-07-01), Kato
patent: 5260783 (1993-11-01), Dixit
"IC Executes Still-Picture Compression Algorithms", by M. Leonard, Electronic Design, May 23, 1991, pp. 49-51 and 53.
"Aufbereitung der Meteosat-2-Signale", by Dr.--Ing. Roland Woitowitz et al, Electronik, vol. 36, Feb. 20, 1987, pp. 92-96.
"Video compression makes big gains" by H. Peng et al, IEEE Spectrum, Oct. 1991, pp. 16-19.
"A Variable Bit Rate Video Codec for Asynchronous Transfer Mode Networks" by W. Verbiest et al, IEEE Journal on Selected Areas in Communications, Jun. 1989, pp. 761-770.

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