Pulse or digital communications – Bandwidth reduction or expansion – Television or motion video signal
Reexamination Certificate
1998-12-31
2001-05-15
Le, Vu (Department: 2713)
Pulse or digital communications
Bandwidth reduction or expansion
Television or motion video signal
Reexamination Certificate
active
06233280
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a device which performs inverse quantization and inverse scanning at high speeds in a high picture quality video decoder for high definition displayes, preferable, and televisions.
2. Discussion of Related Art
In recent years, digital television (TV) broadcasting has been drawing much attention, and much research and development are now devoted to techniques of compressing and transmitting video data to enjoy the screen of high picture quality through televisions. The moving picture experts group-2 (MPEG-2) is normally used as algorithm for compressing video signals, and the compression rate is 1/40 to 1/60. Such algorithm is used to transmit digital data of high picture quality via general broadcasting channel. The digital TV receiver requires a video decoder for recovering the compressed input video data into original high picture quality video data. The video decoder for digital broadcasting must have a data processing rate 5 or 6 times higher compared to common-type video decoders in order to decode video signals of high picture quality.
FIG. 1
is a block diagram of a conventional video decoder which is used to process video signals of general resolution whose volume or data rate is 15 MByte per sec.
A video bit stream applied from an encoder is decoded in a variable length decoder (VLD)
11
to be divided into motion vector, quantization value, DCT coefficient.
A value corresponding to the DCT coefficient of VLD
11
's output is input to inverse discrete cosine transformer (IDCT)
14
through inverse scanner (IS)
12
and inverse quantizer (IQ)
13
. The VLD
11
decodes the DCT coefficient into a run-level pair. That is, a single DCT block is formed of coefficients of 8×8, and only coefficients not 0 of them are in a code. So, VLD
11
produces a level and a run as to the size of coefficients not 0, i.e., how many 0s are inserted between these coefficients.
If the first, fourth, second and third ones of 64 coefficients are 10, 3, 0, and 0, run-level is (0,10) and (3,3). This should be decoded to 10, 0, 0, 0, 3, and as shown in
FIG. 2
, a run-level decoder
21
is needed to change run-level pairs to 64 consecutive DCT coefficients. As shown in
FIG. 3
a,
the decoding of 8×8 coefficients is in zigzag order so as to begin with low frequency signals in transfer to enhance the run-level code, and as shown in
FIG. 3
b,
it is changed to a raster scanning method before IDCT
14
performs IDCT. In order to do this, as shown in
FIG. 2
, a memory
22
for temporarily storing DCT coefficients and an address controller
23
for providing a read/write address to memory
23
are required. Inverse scanning is carried out by changing the read/write address. Memory
22
and address controller
23
correspond to inverse scanner
12
of FIG.
1
. The IQ
13
performs an inverse quantization with respect to 64 DCT coefficients produced from inverse scanner
12
after inverse scanning according to the quantization value, and produces its output to IDCT
14
.
The IDCT
14
performs an IDCT with respect to the DCT coefficients inversely quantized to produce its output to a motion compensator
15
. Motion compensator
15
recovers the output of IDCT
14
to a complete image by using the video signal inversely discrete cosine transformed and the motion vector separated in VLD
11
, and outputs the image to display
16
.
Display
16
rearranges data according to a picture type before producing, or outputs the data directly. The video decoder system based on MPEG-2 employs an external memory such as dynamic random access memory
22
, and DRAM
22
's blocks are divided into read of required data, write of data motion compensated and read of data to be displayed for read/write of the bit stream and motion compensation. Thus, each block of
FIG. 1
has first input first output (FIFO) parts
17
to
20
, and transfers and receives data via memory controller
21
.
The common-type video decoder is used for processing a small volume of data but is not suitable for processing a large volume of data. That is, since the data volume is increased by six times in order to decode video data of MPEG-2 data of more than 93 MBytes per sec. must be processed, and each component has a processing rate six times as fast as the common-type video decoder of FIG.
1
. In addition, the memory size and the data transfer rate used therefor must be increased.
Most DCT coefficients of the compressed bit stream are zero, and while VLD
11
requires 5 to 6 clocks to decode a single block, run-level decoder
21
, producing 64 DCT coefficients, needs 64 clocks. Therefore, VLD
11
is in idle mode when run-level decoder
21
is operating, which is inefficient.
If such a structure is applied to an HDTV, the VLD, the run-level decoder, the inverse scanner, the IQ should operate at clocks of 94 MHz, which applies heavy load to the hardware since the clock frequency is too high to enabled decoding. The inverse scanning using this structure can be performed in serial only, and the internal memory write and read speeds should be very high.
SUMMARY OF THE INVENTION
Accordingly, the present invention is directed to a video decoder for high picture quality that substantially obviate one or more of the problems due to limitations and disadvantages of the related art.
An object of the present invention is to provide a video decoder for high picture quality which can perform a parallel processing when needing high-speed performance, and can consecutively process video data for a given period of time.
Additional features and advantages of the invention will be set forth in the description which follows, and in part will be apparent from the description, or may be learned by practice of the invention. The objectives and other advantages of the invention will be realized and attained by the structure particularly pointed out in the written description and claims hereof as well as the appended drawings.
To achieve these and other advantages and in accordance with the purpose of the present invention, as embodied and broadly described, the present invention provides a video decoder for high definition television including a variable length decoder decoding codes corresponding to discrete cosine transform (DCT) coefficients of an applied video bit stream, and producing a run-level pair for each code; an index decoder storing run-level pairs produced from the variable length decoder, and producing the position information indicating the number of a level value of a corresponding run-level pair among 64 DCT coefficients; an inverse quantizer obtaining an added value corresponding to the position information of the index decoder from a quantization matrix, and performing an inverse quantization by multiplying a quantizer level for determining a quantization step and DCT coefficient to the added value; an inverse scanner including a plurality of memories, and inversely scanning the DCT coefficient inversely quantized and applied serially from the inverse quantizer and producing the DCT coefficient in parallel at the same time; and an inverse discrete cosine transformer performing an inverse discrete cosine transformation (IDCT) of the DCT coefficient produced in parallel from the inverse scanner.
The video decoder of the present invention includes first and second buffers that each consist of a plurality of memories and selectively write applied data into the memories by providing a different write enable signal to each memory while commonly providing data and write address to the plural memories, and commonly applies the read address and read enable signal to a plurality of the memories, thus reading data out of the memories at the same time, and producing the data in parallel. The buffer controller generates a write/read address and a write/read enable signal of the memories by using valid and index signals to write the inversely quantized DCT coefficients into a plurality of the memories one by one, and to simultaneously read the DCT co
Kim Jin Kyeong
Lyu Hwa Young
Fleshner & Kim LLP
Le Vu
LG Electronics Inc.
Vo Tung
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