Video data processing circuit employing plural parallel-to-seria

Details Video data processing circuit employing plural parallel-to-seria Video data processing circuit employing plural parallel-to-seria

1986-07-15

1988-02-23

Chin, Tommy P.

Facsimile and static presentation processing

Facsimile

Specific signal processing circuitry

358 21R, 358280, 364518, H04N 514, H04N 964

Patent

active

047274239

ABSTRACT:
A video data processing circuit eanbles an image to be displayed at a higher resolution on an image display unit such as a CRT display unit without the need for high speed parallel-to-serial (P/S) conversion and high speed accessing to look-up tables. Video data each composed of k bits are read in parallel from first to ith video RAMs (VRAMs) and supplied to a corresponding one of first to jth P/S converters. Each of the first to jth P/S converters parallelly stores those k bit video data. Each of the P/S converters serially outputs the stored video data one by one at a first time interval. The video data from the first P/S converters are supplied to a first look-up table, and similarly the video data from the second P/S converters to jth converters are supplied respectively to second to jth look-up tables. Each of the first to jth look-up tables convert the supplied video data into color data. The color data outputted respectively from the first to jth look-up tables are supplied to a selector which outputs the supplied color data one by one at a second time interval of one jth of the first time interval.

REFERENCES:
patent: 4384336 (1983-05-01), Frankle
patent: 4437121 (1984-03-01), Taylor
patent: 4587558 (1986-05-01), Sugiyama
patent: 4616319 (1986-10-01), Peters

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