Television – Camera – system and detail – Combined image signal generator and general image signal...
Reexamination Certificate
1997-08-14
2002-02-19
Ho, Tuan (Department: 2612)
Television
Camera, system and detail
Combined image signal generator and general image signal...
C358S451000
Reexamination Certificate
active
06348946
ABSTRACT:
This invention relates to video signal acquisition, processing and transmission systems and, more particularly, to such processing systems as video conferencing and other similar systems where large amounts of high volume raw data must be quickly processed in real time.
In video picture signal acquisition and transmitting systems, a video camera generates an analog signal or signals representing the scene detected or viewed by the camera. The signal may represent the scene in monochrome as a shades of gray or it may represent the scene in color by signals for each of the three color separations. e.g., red, green and blue. Analog samples of the signals are processed by one or more charge-coupled devices (CCD's). Each cell in a CCD stores a signal sample and represents a pixel or a color component of a pixel of the scene. An analog-to-digital converter converts the analog signals stored in the charge-coupled device or devices into digital values which are stored in a random access memory (RAM). The digital signals may be stored in a RAM known as a VRAM which is a RAM specifically designed to store digital video signals. The VRAM provides two paths into memory, one for writing digital data into the memory and the other path for reading data out of the memory.
When the video signal is color video, the scene is detected through filters corresponding to the three color separations to generate three color video signals., i.e., a red video signal, a green video signal and a blue video signal. At this point, the analog signal has changed to digital format and is ready for processing. It is stored in digital memory. One memory plane is provided for each color where each memory location corresponds to one pixel. In VRAM or dual port memory, the processor must read the memory and perform the processing algorithm. The common processor which may be a microprocessor or bit slice processor must fetch the data across the data bus and into a register set. Some processors may be scalar or super scalar having the capability of fetching an instruction and performing an instruction within the same clock cycle. Some processors may have floating point processors which have the capability of performing a multiply or divide into two or even one clock cycles. Some processors may have instruction extensions for performing specialized functions. All these processor types still require the read and write cycle to retrieve and store the data from memory. Some processors have the capability of modifying the memory directly but they do so through extended clock cycles and thus offer no throughput advantage. If a way could be found for a processor to look ahead of temporal data in a memory bank without executing bandwidth intensive read write cycles for each memory address then algorithm processing speeds for video conferencing applications could be significantly improved. This invention achieves that purpose.
SUMMARY OF THE INVENTION
The prior art as described above requires a large downstream effort to achieve video data compression. The random access memory array employed in the system of the invention, called a VAM, has the ability to tell the processor information about the temporal nature of the video data without requiring the processor to first read the data and then test the data. In accordance with the present invention, the capability of processing the video data is designed directly in the memory function as they are stored. The memory array, by providing a capacity of temporal processing wherein the digital data produced by the A/D converter in one video frame can be logically interacted with another video frame later in time, can make a significant reduction in the bandwidth required to transmit a video frame. Specifically, in accordance with the invention, each pixel is provided with an addressable memory cell plus additional storage and control registers. Present technology has the ability to pack large amounts of memory storage into a small space. For example, this trend has produced 16 megabyte RAM package from a 1 megabyte package. This invention seeks to take advantage of this increased density capacity, by trading additional RAM density for functional capacity. Typically, one memory location will hold the pixel value at time To and will hold the same pixel at time T
1
. That is one memory location will hold and store the same pixel value from two distinct times. Additionally the memory location will act upon the two values using a processor set criteria. Depending on outcome, the memory location will set a flag and make the outcome results available as data to the processor, all the while the data last written to the memory location is still available as data. The outcome result is a radix reduced representation of the T
1
pixel value. This radix reduced pixel value will allow the use of reduced transmission bandwidth without noticeable lost picture quality.
In accordance with another aspect of the invention having to do with setting the memory cell criteria, the video data is compressed by making use of gray scale mathematics. In this scheme, the luminosity of video data is represented by the difference, plus or minus, from a mid point in the gray scale ranging from a maximum gray scale luminosity, e.g. white, and a minimum luminosity, e.g. black. Note that any monochromatic color value, e.g. red, green or blue, as well as gray scale values, works well with this scheme. The luminosity of regionally located pixels having the same sign are organized in groups and the sign of the luminosity values of the pixels in the group is indicated by the least significant bit of the luminosity value of the first pixel data value of the group. By means of this scheme, further additional bandwidth required to represent the luminosity value is reduced.
In accordance with another aspect of the invention, the video camera in addition to generating color separated pixel values corresponding to a detailed scene also detects a gray scale value. The scene is illuminated with infrared light under video processor control which adds a controlled intensity component to the detected gray scale pixel values. The gray scale values with the infrared component can be used to reduce the distortion caused by illumination of the detected scene within the office environment typically using AC powered flourescent lighting.
In accordance with another aspect of the invention, the purpose of a VAM cell is to off load comparative processing from the computer processor, back plane and bus systems. The processor need only be concerned with identifying image boundaries and image motion from special VAM signals. The VAM cell is capable of generating a signal representing processing results which can then be scanned by the processor at a much higher speed than typical memory read and write operations. The processor then has time to modify and organize the algorithm to meet changing conditions without lost data or delaying data transmission.
Further objects and advantages of the invention will become apparent as the following detailed description of the invention unfolds when taken in consideration with the following drawings.
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Aitken Richard L.
Ho Tuan
Lockheed Martin Corporation
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