Pulse or digital communications – Bandwidth reduction or expansion – Television or motion video signal
Reexamination Certificate
1997-07-23
2001-04-24
Rao, Andy (Department: 2713)
Pulse or digital communications
Bandwidth reduction or expansion
Television or motion video signal
C375S240030
Reexamination Certificate
active
06222885
ABSTRACT:
BACKGROUND OF THE INVENTION
The present invention relates in general to signal compression-decompression (codec) hardware, and in particular to an semiconductor implementation of novel codec circuitry used for interactive video applications and the like.
As the computer is becoming a more common means of human communication and interaction, the demand is rising for the interaction to be more immediate and complete. This has led to the development of technologies that facilitate interactive video and collaborative video applications such as video conferencing. In most cases, the raw data requirements for such applications far exceed available bandwidth, so data compression is necessary to meet the demand.
Most compression schemes operate on digital images that are expressed as a two-dimensional array of picture elements (pixels) each with one (as in a monochrome or gray-scale image) or more (as in a color image) values assigned to a given pixel. Commonly, a color image is treated as a superposition of three independent monochrome images for purposes of compression.
State-of-the-art compression schemes have been promulgated as standards by an international Motion Picture Experts Group; the current standards are MPEG-1 and MPEG-2. MPEG-1 addresses compressed video bitstream of typically between 0.5 to 1.8 MB/s, while MPEG-2 deals with the faster rates of typically 4 to 9 MB/s. These standards involve more complex compression algorithms based on discrete cosine transform, as well as motion compensation techniques to achieve higher compression ratios with higher resolution. As a result MPEG-based compression-decompression (codec) hardware are considerably more expensive. MPEG-2 for example is primarily intended for broadcast TV, where an encoder with a high price tag (in the range of tens of thousands of dollars) serves multitudes of television viewers each with a set-top box. MPEG is therefore suited for limited applications involving playback of video encoded off-line.
For wider consumer applications such as the PC multimedia market, however, MPEG-based codecs are not only prohibitively expensive, their compression effectiveness is non-optimal, encoding requirements excessive, and scalability too limited. To capture and manipulate images in real time, the affordable alternative to the average PC user remains products that can only perform still frame video capture.
There is therefore a need for a cost-effective image compression-decompression system that enables for example computer users to process a continuous stream of video data in real time.
SUMMARY OF THE INVENTION
The present invention offers a more cost-effective system for real time record and playback of motion video through a computer interface port such as a PC-compatible parallel port. Broadly, the invention combines hardware implementing data compression and decompression based on a vector quantization algorithm along with video input/output port and computer interface to enable a PC-type apparatus to process continuous-stream video and audio data in real time. The video compression hardware, according to a preferred embodiment of the present invention, is packaged in a separate plug-in module that externally connects to, for example, a PC-compatible parallel port. In a specific embodiment of the present invention, a customized integrated circuit implementing the compression and decompression algorithms is combined with off-the-shelf video encoder and decoder components as well as one or more memory devices.
Accordingly, in one embodiment, the present invention provides a data compression-decompression (coded) apparatus which includes a video input/output port having an input terminal for receipt of video signal, and an output terminal; codec logic coupled to the video input/output port for implementing hierarchical vector quantization compression-decompression algorithm; and a computer interface having connectors for coupling to a host computer via a computer bus.
In another embodiment, the present invention provides an integrated circuit for compressing and decompressing video data that includes a video port coupled to receive digital component video signal, a scaler and an interpolator coupled between the video port and a first memory interface, a second memory interface coupled to the first memory interface, and a parallel port interface coupled to the second memory interface. The integrated circuit further includes an audio port coupled to the second memory interface, a word wrap block coupled between the second memory interface and the parallel port, and an unwrap block coupled between the second memory interface and the first memory interface.
In yet another embodiment, the present invention provides a system for processing video and audio data including the integrated circuit (IC) as described above, a video encoder and decoder coupled to the video port of the IC, audio encoder and decoder coupled to the audio port of the IC, a first memory unit coupled to the first memory interface of the IC for storing data representing compression tables, and a second memory unit coupled to said second memory interface of the IC for storing intermediate video and audio data.
In a further embodiment, the present invention provides an interactive video station including a computer coupled to a camera, an interface mechanism coupled to the computer, and a plug-in module incorporating the system described above for processing video and audio signals interactively.
A better understanding of the nature and advantages of the video compression and decompression system of the present invention may be had with reference to the detailed description and the diagrams below.
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Chaddha, H., et al., “Hierarchical Vector Quantization of Perceptually Weighted Block Transforms”,IEEE, pp. 3-12, (1995).
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Chaddha Navin
Herzen Brian Von
Wotiz Richard A.
Microsoft Corporation
Rao Andy
Schwegman Lundberg Woessner & Kluth P.A.
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