Radiant energy – Photocells; circuits and apparatus – Photocell controlled circuit
Reexamination Certificate
2001-01-23
2003-10-14
Le, Que T. (Department: 2878)
Radiant energy
Photocells; circuits and apparatus
Photocell controlled circuit
C250S208100
Reexamination Certificate
active
06633029
ABSTRACT:
FIELD OF THE INVENTION
This invention relates generally to a bus and, more particularly, to a video bus for high speed multi-resolution imagers.
BACKGROUND OF THE INVENTION
A solid state imager is a semiconductor device capable of converting an optical image into an electronic signal. Imagers can be arranged in a matrix and utilized to generate video signals for video cameras, still photography, or anywhere incident radiation needs to be quantified. When incident radiation interacts with a photogate, charge carriers are liberated and can be collected for sensing. The number of carriers collected in a photogate represents the amount of incident light impinging on the site in a given time-period.
There are two basic devices with many variants, employed to collect and sense, charge carriers in a photogate. The two basic devices are photodiodes and photogates. Variants of photodiodes include, but are not limited to: Pinned, P-I-N, Metal-Semiconductor, Heterojunction, and Avalanche. Photogate structures include: Charge Couple Devices (CCD), Charge Injection Devices (CID) and their variants that include virtual phase, buried channel and other variations that utilize selective dopants. The selective dopants are used to control charge collection and transfer underneath and between the photogate(s) and the sense node.
The solid state imagers heretofore used have been dominated by CCD's because of their low noise as compared to Photodiodes and CIDs. The low noise advantage of CCD imagers is the result of collecting the photon generated charge at the pixel site and then coupling or shifting the actual charge to an amplifier at the periphery of the array. This eliminates the need for the long polysilicon and metal busses that degrade the signal with their associated resistance and capacitance. However, the low noise of the CCD requires the imager to be read in a fixed format and once the charge is read it is destroyed. The requirement of coupling the collected photon charge from the pixel to the periphery amplifier (a.k.a. CTE), requires proprietary processing steps not compatible with industry standards CMOS or BiCMOS processes.
Solid state imaging devices have developed in parallel with CMOS technology and as a result all imager manufacturers developed their own proprietary processes to maximize imager performance characteristics and wafer yield. Specialized silicon wafer processing kept imager prices relatively high. Linear active pixel sensors have been commercially produced since 1986. Beginning in the early 90's the move to transfer the proprietary processes to an industry standard CMOS processes was on. The advantages of using an industry standard process include: competitive wafer processing pricing, and the ability to provide on chip timing, control and processing electronics. By the end of the year 1992, a 612×512 CMOS compatible, CID imager with a preamplifier and CDS per column had been fabricated. The imager could either be operated as a random access 512×512 CID, or all the columns could be summed together and operated as a linear active pixel sensor.
Area arrays utilizing active pixel sensors in which a photodiode or photogate is coupled to an output source follower amplifier which in turn drives a Correlated Double Sampling (CDS) circuit, where the two outputs of the CDS cell then drives two more source followers circuits that in turn are fed into a differential amplifier are shown in U.S. Pat. No. 5,471,515 which is herein incorporated by reference. This uses source follower circuits, that typically have gains less than unity that vary from one source follower to another. The source follower gain variation is due to variations of FET thresholds. The source follower gain variation results in a pixel to pixel gain mismatch. Also, the active pixel sensors suffer gain variations due to the CDS circuit per column, when the CDS employs a source follower pair to drive its output. The resulting CDS signal and its corresponding offset can have different gains that are not correctable by the differential amplifier. Also, the source follower configuration of active pixel doesn't allow for binning of pixels.
The voltage mode of operation of prior art does not allow for binning, which, is the summation to two or more pixel signals at once.
What is needed is an imager which has the low noise level of a CCD, the random access, and binning of a CID, and uniform gain and response from all pixels; while, maintaining low power, ease of use and high analog video frame rates.
In addition to finding an imager which has the low noise level of a CCD, the random access, and binning of a CID, and uniform gain and response from all pixels, imagers suitable for industrial and/or scientific applications are also needed. Over the last 30 years the CCD sensor and camera electronics technology has evolved to meet most of the demands for industrial and/or scientific applications. However, the resulting cameras require a state-of-the-art, large pixel, multi-port CCD chip plus several extra chips and usually several circuit boards filled with electronics to accomplish this. Thus, the cameras cannot physically fit in certain applications, the power consumed is significant, and the resulting cameras are far too expensive for many applications. The necessary recombination of the video data from several ports, further increases the video processing complexity and ultimately drives-up the cost and size of the video system.
As discussed earlier over the past several years, thanks to design rule shrinkage, image sensors using sub-micron CMOS process technology have become practical. By using CMOS technology for the sensor array itself, the problem of integrating extra circuitry on chip becomes straightforward. Elements such as A/D converters, timing generators, control circuitry and interface circuitry can easily be added. In addition, the operation of CMOS imagers is simplified by the elimination of the need for precise timing and level control of multiple clocks required to drive the large capacitance transfer gates inherent in CCD'S. Even with all of these factors, including the exceptional speed and pico-second gate delays of sub-micron processes, the analog video bandwidth per port has not changed much over the past twenty years.
Active pixel sensors (APS) have been proposed as the means to achieve the flexible benefits of CMOS cameras on a chip. Unfortunately, there are performance issues with the fundamental APS approach that limit its performance and functionality. While these limitations may be acceptable for low-end consumer imaging applications, the demands of scientific, professional and industrial applications have, up until now, been largely unmet by CMOS image sensors.
More specifically, industrial and scientific imaging applications require much higher performance and functionality than that required for low-end consumer imaging products. Many of the applications require high readout speeds for video rate or even faster imaging without sacrificing image quality. In addition to image quality, the applications have come to demand greater functionality in the camera. Features such as flexible shuttering and electronic zoom, random access and selectable region of interest for maximizing frame rates and minimizing data storage (especially useful in tracking applications). Lowering the cost of machine system development is the recent advancement of single chip CMOS cameras. Newly developed CMOS cameras have all the flexibility previously listed, however the analog video bandwidth per port has not changed from the traditional CCD, CID or Photodiode technologies.
Most mega-pixel image sensors, including both CCD imagers and APS imagers, have a maximum pixel rate inadequate to meet the frame rate needs of industrial and scientific imaging. CCD devices are limited by both clocking rates and the speeds of the Correlated Double Sampled (CDS) circuitry. In addition the higher amplifier bandwidth required for higher pixel rates increases noise levels. With the column parallel na
Joyner Michael
Pace Matthew
Vogelsong Thomas
Zarnowski Jeffrey
Le Que T.
Molldrem, Jr. Bernhard P.
Silicon Video, Inc.
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