Video buffer management

Details Video buffer management Video buffer management

2007-02-26

2011-11-01

Harold, Jefferey (Department: 2422)

Television

Receiver circuitry

Tuning

C348S725000, C348S553000, C348S715000, C348S567000

Reexamination Certificate

active

08049821

ABSTRACT:
In one embodiment a video system comprises a first tuner, a first memory buffer coupled to the first tuner to receive a first video signal from the first tuner, a second tuner, a second memory buffer coupled to the second tuner to receive a second video signal from the second tuner, and a controller comprising logic to direct the first video signal from the first memory buffer to an output port, receive a signal to switch the output port from the first memory buffer to the second memory buffer, and in response to the signal, couple the output port to the second memory buffer without disrupting the operations of the first memory buffer.

REFERENCES:
patent: 5729300 (1998-03-01), Ahn
patent: 5801786 (1998-09-01), Song
patent: 6115080 (2000-09-01), Reitmeier
patent: 6335728 (2002-01-01), Kida et al.
patent: 6680754 (2004-01-01), Yim
patent: WO-2007/011356 (2007-01-01), None
patent: WO 2007/011356 (2007-01-01), None

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