Television – Image signal processing circuitry specific to television – A/d converters
Reexamination Certificate
2000-06-30
2002-12-03
Hsia, Sherrie (Department: 2614)
Television
Image signal processing circuitry specific to television
A/d converters
C348S574000
Reexamination Certificate
active
06490005
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
This invention relates in general to analog-to-digital converter systems, and more particularly to a high speed analog-to-digital converter suitable for processing video signals to convert the video signals to a digital representation thereof.
2. Description of Related Art
A variety of electronic devices, such as computers, monitors, flat panel displays, wireless communication devices, to name just a few, utilize high speed electronic signals, e.g., clock signals, video signals, spread spectrum and digital wireless communication signals, etc. A predominant trend in electronic devices is the use of digital signals. As it is well known to those of ordinary skill in the art, there are many advantages to representing electronic signals in digital signal form in many such electronic devices.
An Analog-to-Digital converter (ADC) is typically utilized to sample an analog electronic signal at a point in time and to convert the sampled electronic signal to a digital representation thereof. The ADC, in; one common configuration, typically includes a resistive ladder network electrically coupled to a plurality of comparators that are respectively referenced to a plurality of reference voltages. The ADC compares the voltage amplitude of an input signal to the plurality of reference voltages and provides an output signal that is a digital representation of the input signal at a point in time.
Regrettably, conventional ADC implementations have been typically designed for electronic signaling that is much slower than capable of handling the higher speed video signaling. For high speed signaling applications, such as video signaling, ADCs have unique requirements that in the past have not been met by conventional ADC technology.
First of all, ADCs are coupled to input signals via capacitive networks that tend to build up bias voltages over time. These bias offset voltages defeat the accuracy of the ADC comparators. To counter such offset voltages, prior art systems have utilized auto-zeroing circuits that operate within the cycle of a clock to the ADC. This presented no real problem for slower clock systems because there was plenty of time within the cycle to perform functions in the ADC. Unfortunately, this auto-zeroing function consumes a significant portion of the clock cycle in high speed signaling systems and takes away from the operation of the ADC functions during that significant portion of the clock cycle.
Secondly, there is a constant need for higher precision in the final digital representation that is output from the ADC that is sampling an analog signal. Every additional bit line multiplies the number of comparators by a factor of 2. This in turn increases the expense and complexity of the ADC circuits. Additionally, this increases the power consumption of the ADC circuits thereby decreasing the potential speed of driving these circuits at a given power supply. For very high speed circuits it is imperative to drive the ADC at a maximum speed to track the very high speed signals in video signaling.
Dithering has been used in ADCs for slower signaling to allow sharing of some of the circuitry while providing an additional bit of output from the slower ADC. This dithering of the output bits of the ADC has typically been done to improve the linearity of the outputs of the ADC, and not to increase the resolution of the output of the ADC.
Another technique used to enhance the linearity is by utilizing interpolation between output bits by adding, for example, an interpolated output bit between two normal output bits thereby increasing the total number of output bits available from the ADC. This interpolation has traditionally required significant additional passive and/or active elements to be added to the outputs of the ADC to enhance the number of outputs and thereby the linearity of the output of the ADC.
Although dithering and interpolation have been used in slower ADC circuits to enhance the linearity of an output signal from the ADC, there is still a significant need to provide enhanced resolution at the output of a high speed ADC, such as for processing video signaling.
Thus, there is a need to overcome the disadvantages of the prior art as discussed above, and in particular to improve the quality of conversion of the analog electronic signal to a digital representation thereof.
REFERENCES:
patent: 5696510 (1997-12-01), Paillardet et al.
M. Loinaz, et al., “FA 11.1: A 200mW 3.3W 3.3V CMOS Color Camera IC Producing 352x288 24b Video at 30 Frames/s”, IEEE 1998, pp. 11.1-1.9.
M. Loinaz, et al., “A 200-mW, 3.3-V., CMOS color camera IC Producing 352 x 288 24-b Video at 30 Frames/s”. IEEE Journal of Solid-State Circuits, vol. 33, No. 12, Dec. 1998, pp. 2092-2103.
Chow James
Lay Khin
Steinbach Günter W.
Wen Kenny
Bongini Stephen
Hsia Sherrie
Jorgenson Lisa K.
STMicroelectronics Inc.
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