Vias having varying diameters and fills for use with a...

Active solid-state devices (e.g. – transistors – solid-state diode – Combined with electrical contact or lead – Of specified material other than unalloyed aluminum

Reexamination Certificate

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C257S762000, C438S612000, C438S644000, C438S637000, C438S638000

Reexamination Certificate

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07348671

ABSTRACT:
A method for forming electrical interconnects having different diameters and filler materials through a semiconductor wafer comprises forming first and second openings through a semiconductor, wherein the first opening has a narrower width (smaller diameter) than the second opening. A first conductive material is formed over the semiconductor wafer to completely fill the narrower opening and only partially fill the wider opening. The first conductive material is optionally removed from the wider opening using an isotropic etch. A second conductive material is subsequently formed over the semiconductor to completely fill the wider opening.

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“Wafer Backside Removal to Complete Through-Holes and Provide Wafer Singulation During the Formation of a Semiconductor Device”, Rickie C. Lake, U.S. Patent Application filed Aug. 24, 2004, US Appl. No. 10/925,525.
“Pass Through Via Technology for Use During the Manufacture of a Semiconductor Device”, W. Mark Hiatt, U.S. Patent Appl. filed Aug. 24, 2004, U.S. Application No. 10/925,796.

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