Electricity: conductors and insulators – Conduits – cables or conductors – Preformed panel circuit arrangement
Reexamination Certificate
2001-06-22
2002-11-12
Paladini, Albert W. (Department: 2827)
Electricity: conductors and insulators
Conduits, cables or conductors
Preformed panel circuit arrangement
C174S263000, C029S852000, C361S795000
Reexamination Certificate
active
06479765
ABSTRACT:
BACKGROUND AND SUMMARY OF THE INVENTION
The present invention generally relates to printed circuit boards, and, more particularly, the present invention relates to printed circuit boards having plated vias or holes.
Multilayer printed circuit boards have difficulty carrying high-speed signals through vias. Vias are plated holes in the printed circuit boards used to connect one or more layers together either to change layers for signal routing purposes or to connect them for common grounding. Vias are also used to connect surface mount pads for surface mount components to internal layers, and also for connecting solder tail or press-fit tail components to the boards. The reason vias create difficulties in carrying high-speed signals is that they exhibit stray capacitance within the electrical path because of the plated barrel's proximity to inner conducting layers, such as ground and power layers. This stray capacitance creates an impedance discontinuity relative to the circuit board which causes a portion of the high speed signal to be reflected. These reflections traveling through the transmission system can cause false clocking of the digital signals, and may cause a receiver chip to switch erroneously. To reduce the stray capacitance, one may reduce the length of the plated vias by counterboring the backside of the boards. However, counterboring does not allow routing of signals to layers near the bottom of a printed circuit board stack-up, thus greatly reducing signal routing possibilities. Necking down the vias also reduces the stray capacitance, but only slightly by reducing the surface area of the plated barrel and increasing barrel's separation from other conducting layers.
According to one aspect of the present invention, a method is disclosed for substantially eliminating the stray capacitance exhibited by a via in a printed circuit board by successively milling off adjacent strips of the printed circuit board to provide on each signal layer a strip of exposed contacts for the conductive traces thereon.
According to another aspect of the present invention, a method is disclosed for establishing contacts on a multilayer printed circuit board having a ground, signal, ground, signal and ground stack-up configuration. The individual signal layers have signal pads and conductive traces leading away from the pads. The method includes the steps of: a) drilling blind signal holes in the printed circuit board down to signal pads on successive signal layers, b) drilling through ground holes in the printed circuit board through the ground layers, c) filling the holes with conductive material, and d) removing adjacent strips of the printed circuit board nearly down to successive signal and ground layers to provide on each signal and ground layer a strip of exposed contacts. In accordance with a further aspect of the present invention, the removing step comprises the step of milling off adjacent strips of the printed circuit board nearly down to successive signal and ground layers to provide on each signal and ground layer a strip of exposed contacts.
Most high speed multilayer printed circuit boards carry differential circuits that are edge-to-edge coupled in a stripline configuration (i.e., the layers are alternately ground and signal in a sandwich configuration). The technique of the present invention is particularly suited for this application, although not limited to it.
Additional features of the present invention will become apparent to those skilled in the art upon a consideration of the following detailed description of the preferred embodiments exemplifying the best mode of carrying out the invention as presently perceived.
REFERENCES:
patent: 3400210 (1968-09-01), Reimer
patent: 4935284 (1990-06-01), Puerner
patent: 5774340 (1998-06-01), Chang et al.
patent: 5961349 (1999-10-01), Paagman
patent: 6075211 (2000-06-01), Tohya et al.
Barr Alexander W.
Ramey Samuel C.
Barnes & Thornburg
Paladini Albert W.
Robinson Nugent Inc.
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