VIA0 etch process for FRAM integration

Details VIA0 etch process for FRAM integration VIA0 etch process for FRAM integration

2005-01-11

2005-01-11

Guerrero, Maria F. (Department: 2822)

Semiconductor device manufacturing: process

Having magnetic or ferroelectric component

C438S239000, C438S240000, C438S250000, C438S253000, C438S396000, C438S238000

Reexamination Certificate

active

06841396

ABSTRACT:
A ferroelectric memory device comprises a logic programmable capacitance reference circuit. The circuit is adapted to generate a reference voltage during a sense mode of operation, wherein the reference voltage comprises a value that is a function of one more memory conditions. The memory device further comprises a bit line pair, wherein a first bit line of the bit line pair has a ferroelectric capacitor coupled thereof for sensing thereof, and a second bit line of the bit line pair is coupled to the reference voltage. A sense circuit is coupled to the bit line pair and is configured to detect a data state associated with the ferroelectric capacitor using a voltage associated with the first bit line and reference voltage on the second bit line.

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