Active solid-state devices (e.g. – transistors – solid-state diode – Combined with electrical contact or lead – Of specified material other than unalloyed aluminum
Reexamination Certificate
1999-11-12
2001-12-18
Quach, T. N. (Department: 2814)
Active solid-state devices (e.g., transistors, solid-state diode
Combined with electrical contact or lead
Of specified material other than unalloyed aluminum
C257S762000, C257S765000
Reexamination Certificate
active
06331732
ABSTRACT:
FIELD OF THE INVENTION
The present invention relates generally to integrated circuits and more particularly to a method and system for minimizing diffusion of a high conductivity metal sputtered into a via hole in such a circuit.
BACKGROUND OF THE INVENTION
High conductivity of the interconnects or the metal layers of an integrated circuit is important for the efficient operation of such a circuit, particularly at submicron technologies. In previous integrated circuits, aluminum has been utilized to provide the interconnect for the device. However, as standards for speed have increased, i.e., smaller and smaller process technologies (0.18 &mgr;m and lower), other metals have been used. In a preferred embodiment, high conductivity metal such as copper, gold and platinum have been used as the interconnect to enhance the speed of the device.
High conductivity interconnects in particular are highly desirable for advanced wirings in logic technology. However, high conductivity metals such as copper, gold and platinum have very high diffusivity through several dielectrics. This high diffusivity is a problem because in a typical processing of the device, the metal will get sputtered from a bottom metal layer onto the sidewall of the device. This elemental layer then has to be removed in order to prevent any diffusion from the walls of the via to minimize poisoning of the junction. Conventional chemical processes employed to remove high conductivity metal from the sidewall of the dielelectric material will also remove/attack high conductivity metal at the base of the via. Accordingly, although the high conductivity interconnects increase the overall performance of the device, they also provide challenges in manufacturing the device.
What is needed, therefore, is a system and method which minimizes the poisoning of associated with high conductivity metals that also have high diffusivity. The system and method should be easy to implement and cost effective. The system and method should also be easily adaptable utilizing conventional processing techniques.
The present invention addresses such a need.
SUMMARY OF THE INVENTION
A method and system for providing a via structure for a high conductivity metal of a integrated circuit is disclosed. In a first aspect the method and system comprises etching a photoresist material and a dielectric material down to the high conductivity metal to form a via hole. The via hole includes sputtered high conductivity metal on the sidewalls. The method and system further includes providing a via plug material within the via hole. The vial plug material substantially covers a base portion of the high conductivity metal and the sidewalls of the via hole. The via plug material is also capable of gettering or dissolving the high conductivity metal sputtered on the sidewalls of the dielectric material.
In a second aspect, a via structure for an integrated circuit is disclosed in accordance with the present invention. The via structure includes a high conductivity metal and a dielectric material surrounding the high conductivity metal. The dielectric material includes sidewalls to form a via hole on tope of the high conductivity metal. The via structure further includes a via plug material covering the high conductivity metal and substantially filling the via hole. The via plug material is also capable of gettering or dissolving the high conductivity metal sputtered on the sidewalls of the via hole.
Accordingly, by providing a via plug material within the via hole, the via plug material getters or dissolves the high conductivity metal that reaches the sidewalls of the dielectric layer during the via etch and sputter etch processes and the junction poisoning problems associated therewith are substantially minimized.
REFERENCES:
patent: 4789648 (1988-12-01), Chow et al.
patent: 5019531 (1991-05-01), Awaya et al.
patent: 5305519 (1994-04-01), Yamamoto et al.
patent: 5741626 (1998-04-01), Jain et al.
patent: 5759915 (1998-06-01), Matsunaga et al.
patent: 5817572 (1998-10-01), Chiang et al.
Chen Susan Hsuching
Gupta Subhash
Advanced Micro Devices , Inc.
Quach T. N.
Sawyer Law Group LLP
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