Via structure for semiconductor chip

Active solid-state devices (e.g. – transistors – solid-state diode – Combined with electrical contact or lead – Of specified material other than unalloyed aluminum

Reexamination Certificate

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C257S508000

Reexamination Certificate

active

07042094

ABSTRACT:
A multi-level via structure for a semiconductor chip in which the collective area of a vias structure is not entirely oriented directly in-line with the collective area of an adjacent vias structure. In one embodiment, adjacent via structure areas appear to be crisscrossed in relation to one another and in another embodiment adjacent via structure areas do not coincide at all from a perpendicular perspective.

REFERENCES:
patent: 6236114 (2001-05-01), Huang et al.
patent: 6667552 (2003-12-01), Buynoski

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