Via layout with via groups placed in interlocked arrangement

Details Via layout with via groups placed in interlocked arrangement Via layout with via groups placed in interlocked arrangement

2006-06-19

2008-12-02

Le, Thao P. (Department: 2818)

Active solid-state devices (e.g., transistors, solid-state diode

Combined with electrical contact or lead

Of specified configuration

C257S781000, C257SE23011, C257SE23169, C257S773000

Reexamination Certificate

active

07459792

ABSTRACT:
Via layout with via groups placed in an interlocked arrangement for suppressing the crack propagation along the domain boundary between the via groups. A structure has a metal via pattern located in a dielectric layer and having a first via group and a second via group adjacent to each other. The first via group has at least two first line vias extending in a first direction, and the second via group has at least two second line vias extending in a second direction. The first via group and the second via group are placed in an interlocked arrangement, and a domain boundary along the first direction or the second direction between the first via group and said second via group is not straight.

REFERENCES:
patent: 6822329 (2004-11-01), Varrot et al.
patent: 7295745 (2007-11-01), Uchida
patent: 7323784 (2008-01-01), Yiu et al.
patent: 2001/0009802 (2001-07-01), Lee
patent: 2003/0073257 (2003-04-01), Watanabe
patent: 2004/0021227 (2004-02-01), Watanabe
patent: 2008/0081461 (2008-04-01), Lee et al.

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