Via hole having fine hole land and method for forming the same

Details Via hole having fine hole land and method for forming the same Via hole having fine hole land and method for forming the same

2006-07-12

2009-12-08

Monbleau, Davienne (Department: 2893)

Active solid-state devices (e.g., transistors, solid-state diode

Combined with electrical contact or lead

Of specified configuration

C257SE23015

Reexamination Certificate

active

07629692

ABSTRACT:
A via hole having a fine hole land includes a first conductive layer formed on an inner wall of the via hole, the first conductive layer being in contact with a hole formed in an insulation layer and extendedly projected to the outside and having the same diameter as the hole in the insulation layer; a second conductive layer contacted with the first conductive layer and formed on an inner wall thereof and projected to the outside and having the same height as the first conductive layer; and a circuit line, formed on the insulation layer, to connect the first conductive layer extendedly projected to the outside of hole in the insulation layer, where the second conductive layer has the same height as the first conductive layer and the fine hole land is connected to wire bonding pad or solder ball pad through the circuit line.

REFERENCES:
patent: 5495665 (1996-03-01), Carpenter et al.
patent: 2005/0124196 (2005-06-01), Olson et al.
patent: 2005/0241954 (2005-11-01), Iwanami
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patent: 2004-303856 (2004-10-01), None
U.S. Appl. No. 12/068,457, filed Feb. 6, 2008, Chong Ho Kim, Samsung Electro-Mechanics, Co., Ltd.
U.S. Office Action mailed Apr. 28, 2009 in corresponding U.S. Appl. No. 12/068,457.
U.S. Office Action mailed Oct. 7, 2008 in corresponding U.S. Appl. No. 12/068,457.

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