Via formation in polymeric materials

Details Via formation in polymeric materials Via formation in polymeric materials

1995-06-07

2001-02-13

Chaudhuri, Olik (Department: 2814)

Active solid-state devices (e.g., transistors, solid-state diode

With means to control surface effects

Insulating coating

C257S642000, C257S759000, C438S623000

Reexamination Certificate

active

06188125

ABSTRACT:

FIELD OF THE INVENTION
This invention relates generally to the fabrication of semiconductor devices, and more particularly to methods and structures for using organic-containing materials as intra/interlevel dielectrics.
BACKGROUND OF THE INVENTION
Semiconductors are widely used in integrated circuits for electronic devices such as computers and televisions. These integrated circuits typically combine many transistors on a single crystal silicon chip to perform complex functions and store data. The need to integrate more functions and more storage capacity onto a chip has caused the semiconductor industry to search for ways to shrink, or scale, the size of individual transistors and other devices commonly integrated on a chip. However, scaling devices to smaller dimensions can create a multitude of undesirable effects. One of these effects is an increase in the capacitive coupling between conductors in a circuit, since the capacitive coupling is inversely proportional to the distance between the conductors. This coupling may limit the ultimate speed of the device or otherwise inhibit proper device operation, if steps are not taken to reduce the coupling.
The capacitance between conductors is also highly dependent on the insulator, or dielectric, used to separate them. Conventional semiconductor fabrication commonly employs silicon dioxide as a dielectric, which has a dielectric constant of about 3.9. Many alternate materials have been used or suggested as a way of providing a lower dielectric constant. One such group of materials is organic polymer-containing dielectrics.
SUMMARY OF THE INVENTION
Organic-containing dielectric materials possess many desirable qualities, but it is herein recognized that they are plagued by problems which make their use difficult. One of the problems related to the use of organic-containing dielectrics is that they are generally removed by the same etching procedures commonly used to remove photoresist (a temporary material which is deposited on semiconductor devices to create patterns for various device layers). Other problems with organic-containing materials are the difficulty in adhering contact metal to them, and the possibility of organic-containing materials out-gassing during deposition of adjoining contact metal and reacting with the metal.
The present invention provides a method and structure for creating organic-containing dielectric layers which contain vias on a semiconductor device, allowing electrical connections between conductors above and below the dielectric layer. The present invention uses a novel combination of processing steps to create lined vias through organic-containing dielectrics, thereby both enhancing compatibility with metal processing and preventing damage to the organic-containing dielectrics by subsequent photolithography steps. The organic-containing dielectrics are also desirable because of their relatively low dielectric constant, compared to silicon dioxide dielectrics.
The present invention provides a method for fabricating dielectrics for semiconductor devices with reduced dielectric constant, compared to conventional oxide fabrication techniques, while maintaining compatibility with common semiconductor metal deposition and photlithography materials and techniques. The method can comprise forming a layer of patterned conductors on a substrate, where the substrate may be an actual semiconductor substrate or a previous interlayer dielectric, covering the patterned conductors and substrate with a layer of organic-containing material, and depositing an inorganic cap layer of a material such as SiO
2
over the organic-containing layer. The method can further comprise etching of vias through the cap layer and the organic-containing layer, depositing an inorganic conformal passivating layer over all exposed surfaces, and removing the passivating layer from horizontal surfaces, including the top surface of the cap layer and the bottoms of the vias. This creates a passivating liner which can provide physical isolation for the organic-containing dielectric during subsequent metal deposition or photoresist strip processing steps. One possible variation of the method can provide a total encapsulation of the organic-containing material by an inorganic material such as oxide, preventing contact between the organic-containing dielectric and the underlying conductors also.
Preferably, the organic-containing material is an organic polymer, such as parylene or a polyimide. The organic-containing material may also be a polymer-containing oxide which can be applied as an SOG (spin-on glass), such as the Allied Signal 500 series. The cap layer and passivating layer(s) are preferably composed of inorganic materials such as silicon nitride or compounds containing at least 95% silicon dioxide by weight.
A semiconductor device according to the present invention can comprise a layer of patterned conductors formed on a substrate, where the substrate can be an actual semiconductor substrate or a previously deposited interlayer dielectric, with an organic-containing dielectric layer substantially filling the spaces between and covering the conductors to a depth at least 50% of their height. The device can further comprise a cap layer composed of inorganic material deposited over the organic-containing layer, and at least one via etched through the cap layer and organic-containing layer for the purpose of allowing contacts to be made to the conductors. The device can further comprise a passivating layer deposited on the exposed portions of the organic-containing layer in the vias, and conducting material deposited in the vias so as to provide electrical connections to the patterned conductors.


REFERENCES:
patent: 4523372 (1985-06-01), Balda et al.
patent: 5103288 (1992-04-01), Sakamoto et al.
patent: 5155576 (1992-10-01), Mizushima
patent: 5284801 (1994-02-01), Page et al.
patent: 0 177 845 (1986-04-01), None
patent: 3-27551 (1991-02-01), None
patent: 6097299 (1992-11-01), None
IBM Technical Disclosure Bulletin, “Lithographic Patterns with a Barrier Liner,” vol. 32, No. 10 B Mar. 1990, pp. 114-115.
Thin Solid Films, Sep. 25, 1993, Switzerland, vol. 232, No. 2, ISSN 0040-6090, pp. 256-260, Kubono A. Et al., Direct Formation of Polymide Thin Films by Vapor Deposition Polymerization.
08/234,100 Havemann filed Apr. 28, 1994.

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