Via-filling and planarization technique

Details Via-filling and planarization technique Via-filling and planarization technique

1988-10-11

1990-09-11

Hearn, Brian E.

Fishing, trapping, and vermin destroying

437195, 437228, 156636, 156645, H01L 21321, H01L 21304

Patent

active

049563130

ABSTRACT:
A method of forming a plurality of conductive studs within a non-planar insulator layer (e.g., PSG or BPSG) disposed between a first series of conductive structures arranged on a substrate and metal lines formed on the upper surface of the insulator layer. Vertical vias are defined through the insulator layer to expose at least one of the first conductive structures on the substrate. A conformal metal layer (e.g., CVD W) is deposited on the insulator layer to fill the vias. Then, the metal layer and the insulator layer subjected to a polish etch in the presence of an abrasive slurry, to remove portions of the metal layer outside of the vias while simultaneously planarizing the insulator layer.

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Beyer et al., "Glass Plananrization Stop-Layer Polishing," IBM TDB, vol. 27, No. 8, Jan. 1985, pp. 4700, 4701.

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