Via etch process

Details Via etch process Via etch process

2007-12-04

2007-12-04

Kackar, Ram N. (Department: 1763)

Adhesive bonding and miscellaneous chemical manufacture

Differential fluid etching apparatus

With measuring, sensing, detection or process control means

C156S345250, C438S714000, C438S701000, C438S640000, C438S638000, C438S734000, C438S978000, C216S017000, C204S192100

Reexamination Certificate

active

10854541

ABSTRACT:
Systems and techniques relating to etching vias in integrated circuit devices, in one implementation, include: providing a dielectric material and a conductive material, removing a first portion of the dielectric material to form a hole in the dielectric material, performing a tapering etch that removes a second portion of the dielectric material to form a via that touches down on the conductive material, and laterally expanding a bottom dimension of the via without a significant increase in a depth of the via. The technique can also include: providing a substrate with the dielectric material and the conductive material attached without an associated etch stop layer, removing the first portion at a high etch rate, controlling ion bombardment and plasma chemistry to form a sloped bottom of the via, and performing an intensive ion bombarding plasma etch, laterally expanding the via bottom.

REFERENCES:
patent: 5702562 (1997-12-01), Wakahara
patent: 10335309 (1998-12-01), None
Ping Wang, “Aniso-/Iso-/Anisotropic Via Process for Submicron Device Metal Interconnect”, Motorola Inc., Technical Developments; vol. 19, Jun. 1993,pp. 146-147.

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