Active solid-state devices (e.g. – transistors – solid-state diode – Housing or package – For plural devices
Reexamination Certificate
2000-05-26
2002-02-05
Chaudhuri, Olik (Department: 2814)
Active solid-state devices (e.g., transistors, solid-state diode
Housing or package
For plural devices
C257S738000, C257S779000, C257S780000, C361S764000, C361S783000, C361S792000, C174S255000
Reexamination Certificate
active
06344688
ABSTRACT:
BACKGROUND OF THE INVENTION
(1) Field of the Invention
This invention relates to a multi-chip--package for active and/or passive devices. The devices are joined to a flexible tape which is then joined to a substrate having a cavity such that the devices are within the cavity.
(2) Description of the Related Art
Ultra Large Scale Integration, ULSI, packaging is discussed in a book by C. Y. Chang and S. M. Sze entitled “ULSI Technology”, 1996, The McGraw-Hill Companies, Inc., pages 573-582.
U.S. Pat. No. 5,150,274 to Okada et al. describes a multi-channel module with a plurality of chips mounded on a multilayer circuit board.
U.S. Pat. No. 5,620,928 to Lee et al. shows an ultra thin ball grid array using a flex tape or printed wiring board.
U.S. Pat. No. 5,648,679 to Chillara et al. describes a dielectric flex tape substrate defining a predetermined array of electrically conductive traces and an array of solder balls or solder columns electrically connected to the bottom surface of the flex tape substrate and the traces. An integrated circuit chip having a series of input/output pads is supported on the substrate.
U.S. Pat. No. 5,602,419 to Takeda et al. describes a chip carrier semiconductor device comprising a semiconductor chip having a surface on which a plurality of contact pads, a tape carrier overlying the semiconductor As chip and a plurality of leads provided on the tape carrier overlying the semiconductor chip.
U.S. Pat. No. 5,239,448 to Perkins et al. describes the formation of multichip modules. The invention shows a multichip module carrier that is constructed on a flex carrier, along with other components to form a subsystem.
U.S. Pat. No. 5,147,210 to Patterson et al. describes a first pattern of electrical conductors on a first electrical component and a second pattern of electrical conductors on a second electrical component.
A paper by A. Aintila et al. entitled “Electroless Ni/Au Bumps for Flipchip-on-Flex and TAB Applications”, 1994 IEEE/CMPT Int'l Electronics Manufacturing Technology Symposium, pages 160-164 describes an electroless Ni/Au wafer bumping process.
A paper by R. W. Johnson et al. entitled “Adhesive Based, Flip Chip Technology for Assembly on Polyimide Flex Substrates”, 1997 International Conference on Multichip Modules, pages 81-86 describes research conducted to develop and evaluate isotropically conductive adhesive preforms.
A paper by P. Elenius entitled “Flex on Cap-Solder Paste Bumping”, 1997 International Symposium on Advanced Packaging Materials, pages 115-116 describes the capabilities and reliability results of the Flex on Cap solder bumping process.
A paper by R. Aschenbrenner et al. entitled “Flip Chip Attachment Using Anisotropic Conductive Adhesives and Electroless Nickel Bumps”, 1996 IEEE/CMPT Int'l Electronics Manufacturing Technology Symposium, pages 26-33 describes studies carried out on electrical and mechanical performance of two types of anisotropic adhesives.
A paper by A. F. J. Baggerman et al. entitled “Reliable Au-Sn Flip Chip Bonding on Flexible Prints”, 0569-5503/94/0000-0900 1994 IEEE, 1994 pages 900-905 describes Au-Sn flip chip bonding of integrated circuit chips on flexible polyimide prints.
A paper by C. S. Milkovich et al. entitled “Double Sided Flexible Carrier with Discretes and Thermally Enhanced FCA/COF”, 0569-5503/93/0000-0016 1993 IEEE, 1993, pages 16-21 describes an electronic assembly using SMT components, wire bonded chips as well as area array chips attached to a flexible carrier.
SUMMARY OF THE INVENTION
Current Multi-Chip-Package designs call for a number of types of manufacturing technology such as silicon technology, ceramic technology, lamination technology, bonding technology and the like. The integrated circuit chips or other devices are attached using technologies such as Wire-Bonding, Flip-Chip technology or the like. With chip thicknesses of about 0.025 inches, substrate material thicknesses of about 0.050 inches, input/output pin heights of about 0.15 inches, and over-mold height required for module encapsulation of about 0.025 inches a typical multi-chip-package height or thickness is about 0.25 inches.
Multi-chip-packages are used in a number of applications where the package thickness is an important constraint such as wireless hand held telephones, electronic notebooks, lap top computers, pagers, PCMIA cards, and the like. These applications require packages with a very low profile.
It is a principle objective of this invention to provide a low cost method of forming a multi-chip-package having a very low profile where the elements of the package are testable before final assembly.
It is another principle objective of this invention to provide a low cost multi-chip-package having a very low profile.
These objectives are achieved by using a flexible tape and a substrate having a number of cavities formed at the chip locations. The flexible tape has a number of device blocks, a number of interconnect pads surrounding each device blocks, and a number of test pads. Integrated circuit chips or other devices are joined to the flexible tape in the device blocks. The interconnect pads and the test pads are connected to the integrated circuit chips or other devices by electrodes on or within the flexible tape. The test pads can be used to test the flexible tape with integrated circuit chips and other devices attached before joining the flexible tape to the substrate. The substrate has a number of cavities, with a cavity to match each device block on the flexible tape, and a number of peripheral pads surrounding each cavity. The flexible tape is then joined to the substrate by joining the interconnect pads on the flexible tape to the peripheral pads on the substrate so that the integrated circuit chips and other devices joined to the flexible tape fit into the cavity of the substrate. The peripheral pads on the substrate are connected to plated through holes through the substrate and connected to input/output pads on the back of the substrate.
REFERENCES:
patent: 5147210 (1992-09-01), Patterson et al.
patent: 5150274 (1992-09-01), Okoda et al.
patent: 5239448 (1993-08-01), Perkins et al.
patent: 5602419 (1997-02-01), Takeda et al.
patent: 5620928 (1997-04-01), Lee et al.
patent: 5648679 (1997-07-01), Chillara et al.
patent: 6100112 (2000-08-01), Amano et al.
patent: 6100113 (2000-08-01), Wang
patent: 6200824 (2001-03-01), Hashimoto
Chang et. al, “ULSI Technology”, The McGraw-Hill Corporation, 1996 p 573-582.
Baggerman et al, “Reliable Au-Su Flip Chip Bonding on Flexible Prints”, 0569-5503/9410000-09001994, IEEE, 1994, p 900-905.
Milkovich et al. “Double-Sided Flexible Carrier with Discretes and Thermally Enhanced FCA/COF,” 0569-5503/93/0000-0016, 1993 IEEE, p 16-21.
A. Aintila et al, “Electroless Ni/Au Bumps for Flip Chip-on-Flex and TAB Applications”, 1994 IEEE/CMPT Int'l Electroless Manufacturing Technology Symposium, p 160-164.
“Adhesive Based Flip Chip Technology for Assembly on Polymide Flex Substrates”, 1997, International Conf. on Multichip Modules, p81-86.
Peter-Elenius,“ Flex on Cap-Solder Paste Bumping”, 1997 International Symposium on Advanced Packaging Materials, p115-116.
R. Aschenbrennen, “Flip Chip Attactment Using Anisotropic Conductive Adhesives and Electroless Nickel Bumps” 1996 IEEE/CPMT Int'l Electronics Manufacturing Tech Sym. p26-33.
Ackerman Stephen B.
Chambliss Alonzo
Chaudhuri Olik
Institute of Microelectronics
Prescott Larry J.
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