Very low voltage inter-chip CMOS logic signaling for large numbe

Details Very low voltage inter-chip CMOS logic signaling for large numbe Very low voltage inter-chip CMOS logic signaling for large numbe

1993-01-25

1994-05-10

Westin, Edward P.

Electrical transmission or interconnection systems

Nonlinear reactor systems

Parametrons

307443, H03K 90177

Patent

active

053110838

ABSTRACT:
A CMOS integrated circuit (IC) device
embodiment of the present invention comprises an internal logic circuit operating with traditional 3.3 volt or five volt internal logic levels, an output buffer to convert the internal logic levels to external logic levels of 0.3 volts and an input buffer to convert the 0.3 volt external logic levels to the internal logic levels. In a CMOS IC device having numerous external output loads including relatively high capacitive values that are driven at very high clock rates, the restricted voltage swings of the 0.3 volt external logic levels permit unusually large numbers of devices to be driven without exceeding a predetermined power dissipation limit of the CMOS IC device. The low external logic levels further permit electrostatic discharge (ESD) protection to be included on all signal inputs and outputs of the CMOS IC device. The ESD protection comprises a pair of opposite polarity silicon PN junction diodes in parallel and connected between each signal line and a ground reference.

REFERENCES:
patent: 4527079 (1985-07-01), Thompson
patent: 5023487 (1991-06-01), Wellheuser
patent: 5023488 (1991-06-01), Gunning
patent: 5049763 (1991-09-01), Rogers
patent: 5245224 (1993-09-01), Suzuki
Trevor Marshall, "Fast Transit," Byte magazine, Oct. 1992, pp. 122-136.

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