Very low-power comparison device

Details Very low-power comparison device Very low-power comparison device

2001-03-15

2002-03-12

Tran, Toan (Department: 2816)

Miscellaneous active electrical nonlinear devices, circuits, and

Specific signal discriminating without subsequent control

By amplitude

C327S067000, C327S563000

Reexamination Certificate

active

06356121

ABSTRACT:

FIELD OF THE INVENTION
The present invention relates to the field of electronic circuits, and, more particularly, to low-power comparison devices. The present invention is particularly well suited for applications in which power consumption is limited, especially in electronic equipment powered by a battery.
BACKGROUND OF THE INVENTION
One application in which comparison devices with low power consumption are used is the biomedical field, such as in portable equipment or sensors. In this application, the electronic equipment should consume as little power as possible because the total current available is very limited. One microampere typically corresponds to an available order of magnitude.
When the consumption of an electronic device is reduced, its performance characteristics are generally reduced as well. This is especially the case with comparison devices. To reduce their consumption, the bias current is typically reduced. Yet, the more the bias current is reduced, the lower the efficiency of these devices. That is, their switch-over operation becomes very slow. For example, a standard prior art comparator, biased at 60 microamperes, switches over in about one hundred nanoseconds. When biased at 500 nanoamperes, it will switch over in six microseconds.
A prior art comparison device for comparing two weak signals M
1
and P
1
applied at its input is shown in
FIG. 1
in an exemplary metal oxide semiconductor (MOS) technology embodiment. In general, one of the two signals is a reference signal. The signal MI is a reference signal with a level assumed to be constant, and the signal PI is a signal with a variable level given by any unspecified electronic circuit (not shown). This circuit may, for example, be a measurement circuit.
When weak signals have to be compared, the comparison device usually includes two series-connected comparators, namely a first comparator to amplify the signals to be compared followed by a second comparator with a very high gain. The comparison device illustrated in
FIG. 1
thus includes a first comparator COMP
1
with differential outputs A and B followed by a second comparator COMP
2
with very high gain that delivers a logic signal OUT at its output. The output logic level indicates which of the input signals MI or PI is greater than the other one.
The signal MI is applied to the non-inverting input e+ of the first comparator and the signal PI is applied to the inverting input e−. The first arm of the comparator COMP
1
, associated with the non-inverting input e+, includes a first MOS transistor M
1
mounted as a diode with its gate and drain connected. The first MOS transistor M
1
is series-connected with a second MOS transistor M
2
between the power supply voltage V
PLUS
and a current bias node N
1
. The second transistor M
2
receives the signal MI at its gate. The second arm of the comparator COMP
1
, associated with the inverting input e−, similarly includes a first MOS transistor M
3
mounted as a diode with its gate and drain connected. The first MOS transistor M
3
is series-connected with a second MOS transistor M
4
between the power supply voltage V
PLUS
and the current bias node N
1
. The second transistor M
4
receives the signal PI at its gate.
The comparator COMP
1
further includes a current generator
1
connected between the bias node N
1
and the power supply voltage V
MINUS
. In this configuration, if the level of the signal MI is greater than that of the signal PI, the current in the first arm of the comparator COMP
1
gradually rises from 0 to the bias current level Ip
1
(which the current generator
1
can provide) while no current flows in the second arm.
The very-high-gain comparator COMP
2
, which is not illustrated in detail in
FIG. 1
, includes a first amplifier stage with differential inputs followed by a direction stage and an output stage to reshape the signal. The differential input amplifier stage is biased by a current Ip
2
given by a current generator. In practice, Ip
1
may be equal to Ip
2
. Thus, in the second comparator COMP
2
, since the current Ip
2
is also very low (i.e., in the range of 500 nanoamperes), the switch-over is also very slow.
SUMMARY OF THE INVENTION
An object of the invention is to improve the switch-over performance characteristics of a comparator under low bias current.
Yet another object of the invention is to provide a very low power comparison device with improved switch-over speed.
Referring again to
FIG. 1
, the basic idea of the invention is to use the current flowing into an arm of the first comparator and apply it with a multiplier coefficient to the second comparator as a complement of the current Ip
2
. Thus, the switch-over is accelerated in the second comparator, enabling a substantial improvement of the performance characteristics of the comparison device. Thus, if a device is provided within the comparison device for copying and providing an additional supply of current from the first arm of the comparator COMP
2
as an additional bias current in the comparator COMP
2
, the corresponding switch-over is accelerated to a signal level PI which becomes lower than that of the signal MI.
To accelerate the reverse switch-over, when the level of the signal PI becomes greater than that of the signal MI, it is necessary to provide a similar device on the other arm of the comparator COMP
1
. Once the comparator COMP
2
has changed over, the bias current is again at its maximum level, corresponding to the sum of the bias current Ip
2
of the second comparator and the bias current Ip
1
of the first comparator multiplied by the multiplier factor K. Since there is no need for the current outside the zones close to the switch-over, each additional current supply device may be cut off as soon as the output of the comparison device has changed over to the corresponding direction. Thus, for each additional-current supply device, a switch controlled by the appropriate logic level of the output signal of the comparison device may be used.
According to the invention, a device for comparing two input signals includes a first comparator with differential outputs to whose inputs the signals are applied. The first comparator is followed by a second comparator delivering an output logic signal of the device. Each comparator includes at least one input differential stage, and each stage has two arms biased by a bias current generator. The comparison device may also include at least one additional current supply circuit associated with an arm of the input differential stage of the first comparator to copy the current of the arm and add it, with a multiplier factor, to the bias current of the input differential stage of the second comparator. This facilitates a corresponding switch-over.


REFERENCES:
patent: 5475323 (1995-12-01), Harris et al.
patent: 5734272 (1998-03-01), Belot et al.
patent: 5754076 (1998-05-01), Kimura
patent: 5909136 (1999-06-01), Kimura
patent: 6127868 (2000-10-01), Phillips
patent: 0597420 (1994-05-01), None
patent: 0776087 (1997-05-01), None
patent: 0915562 (1999-05-01), None
Shin et al., Design of a Programmable Slew-Rate Op Amp, Proceedings of the Midwest Symposium on Circuits and Systems, US, New York, IEEE, vol. SYMP. 37, Aug. 3, 1994, pp. 142-146, XP000531995.

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