Very low current pierce oscillator

Oscillators – Solid state active element oscillator – Transistors

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Details

331116FE, 368159, H03B 536

Patent

active

043607896

ABSTRACT:
A very low current Pierce oscillator has two pairs of complementary field-effect transistors (FET's) and a two-terminal quartz crystal. The gates of the first complementary FET pair are coupled through individual capacitors to one terminal of the quartz crystal, their drains being connected together and to the other quartz crystal terminal. Current flow through the crystal oscillator is minimized by a novel oscillator bias loop connected between the gates of the first FET pair. Amplification is provided by the second FET pair which have a commonly connected drain comprising the oscillator output node. The gates of the second FET pair are each connected to a respective one of the gates of the first FET pair. The oscillator bias loop minimizes the source-to-drain current through the first FET pair by reducing the P-channel FET gate voltage in response to the source-to-drain current. The oscillator bias loop assures reliable start-up by permitting the oscillation of the source-to-drain current to increase freely to some large magnitude and then operates to reduce the amplitude of the oscillation and also the dc bias level of the current to an equilibrium condition. Means are provided for preventing elements within the oscillator bias loop from overloading the oscillator or otherwise preventing the initiation of oscillation at start-up.

REFERENCES:
patent: 3902141 (1975-08-01), Berney
patent: 4013797 (1977-03-01), Vittoz
patent: 4039973 (1977-08-01), Yamashiro
patent: 4095195 (1978-06-01), Saito
patent: 4106278 (1978-08-01), Yasada
patent: 4211985 (1980-07-01), Yamashiro
RCA COS/MOS Integrated Circuits Manual, RCA Solid State Division, Summerville, N.J., 1971, pp. 138-148.

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