Very large scale integrated circuit for performing bit-serial ma

Details Very large scale integrated circuit for performing bit-serial ma Very large scale integrated circuit for performing bit-serial ma

1996-11-01

1998-09-08

Mai, Tan V.

Boots, shoes, and leggings

36472502, G06F 700, G06F 1714

Patent

active

058054766

ABSTRACT:
A very large scale integrated circuit for performing a bit-serial matrix transposition operation, comprising an input shift register module for inputting N multiplied results of two N.times.N matrixes in the unit of k bits and outputting them in the unit of k/N bits in response to a load signal, a bit-serial transposition module for selecting k/N-bit data from the input shift register module in response to a switching control signal, an output multiplexer module for selecting k/N-bit data from the bit-serial transposition module in response to the switching control signal, and an output register module for inputting output data from the output multiplexer module in the unit of k/N bits and outputting N data in the unit of k bits. According to the present invention, when an N.times.N matrix transposition operation is performed, the operation occupancy of transposition cells becomes 100% after an N-input delay occurs. Also, the processing unit of data becomes smaller by using a bit-serial processing algorithm. Therefore, the high-speed operation can be performed. Further, the number of gates can be reduced in the integrated circuit. Moreover, because the integrated circuit has a pipelined structure, it is applicable to a multi-dimensional signal processing system requiring a high-speed processing operation.

REFERENCES:
patent: 5177704 (1993-01-01), D'Luna
patent: 5481487 (1996-01-01), Jang et al.
patent: 5644517 (1997-07-01), Ho

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