Very large scale bipolar integrated circuit process

Details Very large scale bipolar integrated circuit process Very large scale bipolar integrated circuit process

1988-01-11

1989-09-12

Hearn, Brian E.

Fishing, trapping, and vermin destroying

437 33, 437241, 437228, 148DIG10, 148DIG11, 357 35, 357 59, H01L 21265

Patent

active

048660019

ABSTRACT:
A bipolar VLSI process includes masking and patterning, implanting a P+ channel stop and locally oxidizing a lightly P-doped, monolithic silicon substrate to define a long, narrow collector region. An N-type collector is implanted in the collector region. The implants are diffused to form a shallow gradient P-N junction. Then, device features requiring a predetermined spacing and size are photolithographically defined along the length of the collector region. The device features and the collector region are made long enough for the features to readily transect the collector region even if the mask is misaligned. The active transistor and the collector, base and emitter contacts are self-aligned with the collector region so as to take advantage of the noncritical spacing of the preceding steps. A single polysilicon layer used to form base, collector and emitter contacts and a triple diffusion transistor. Portions of the substrate silicon and polysilicon are locally oxidized to isolate the contacts and to define emitter width. The width of the collector region defines emitter length.

REFERENCES:
patent: 4276543 (1981-06-01), Miller et al.
patent: 4433471 (1984-02-01), Ko et al.
patent: 4495010 (1985-01-01), Kranzer
Pickett, J. M., "A Fully Self-Aligned Silicon MESFET Process," IEEE, 1981, pp. 123-126.
Buie, J., "Improved Triple Diffusion Means Densest ICs Yet," Electronics, Aug. 7, 1975, pp. 101-106.

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