Very fast variable input multi-bit adder

Details Very fast variable input multi-bit adder Very fast variable input multi-bit adder

1992-02-26

1993-05-11

Smith, Jerry

Boots, shoes, and leggings

G06F 750

Patent

active

052107116

ABSTRACT:
A method and apparatus for quickly adding at least three multi-bit binary numbers. The addition is divided into two stages. In Stage I, each of the addends are grouped into like-ordered multi-bit clusters and the corresponding clusters of the addends are added together using Programmable Read Only Memory (PROM) integrated circuits (ICs) yielding several intermediate sums. In Stage II, the intermediate sums are combined to yield a final sum using Programmable Array Logic (PAL, PAL is a trademark of Monolithic Memories, Inc.) ICs. Furthermore, the final sum is rounded in Stage I (and clipped if necessary in a third stage) before being provided as output. Clipping is achieved by setting the output sum to zero if the final sum is negative and setting the output sum to a predetermined threshold value if the final sum exceeds the threshold value.

REFERENCES:
patent: 3535502 (1970-10-01), Clapper
patent: 3906211 (1975-09-01), Glaser
patent: 5134579 (1992-07-01), Oki et al.

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