Very dense integrated circuit package

Details Very dense integrated circuit package Very dense integrated circuit package

1997-04-28

1998-09-29

Ngo, Ngan V.

Active solid-state devices (e.g., transistors, solid-state diode

Housing or package

Outside periphery of package having specified shape or...

257684, 257724, H01L 2904, H01L 2306

Patent

active

058148850

ABSTRACT:
An integrated circuit package including a carrier having a surface topography of projections or recesses for supporting individual semiconductor circuit chips having a conversely matching bottom surface topography to permit self-aligned positioning of the chip on the carrier.

REFERENCES:
patent: 4489364 (1984-12-01), Chance et al.
patent: 4542397 (1985-09-01), Biegelsen et al.
patent: 4670770 (1987-06-01), Tai
patent: 4709468 (1987-12-01), Wilson
patent: 4783695 (1988-11-01), Eichelberger et al.
patent: 4884122 (1989-11-01), Eichelberger et al.
patent: 4933042 (1990-06-01), Eichelberger et al.
patent: 4949148 (1990-08-01), Bartelink
patent: 4967146 (1990-10-01), Morgan et al.
patent: 5019535 (1991-05-01), Wojnarowski et al.
patent: 5023205 (1991-06-01), Reche
patent: 5034091 (1991-07-01), Trask et al.
patent: 5061987 (1991-10-01), Hsia
patent: 5091330 (1992-02-01), Cambou et al.
patent: 5168344 (1992-12-01), Ehlert et al.
patent: 5207866 (1993-05-01), Lue et al.
patent: 5331203 (1994-07-01), Wojnarowski et al.
patent: 5353498 (1994-10-01), Fillion et al.
patent: 5355102 (1994-10-01), Kornrumpf et al.
patent: 5373627 (1994-12-01), Grebe
patent: 5432681 (1995-07-01), Linderman
patent: 5521420 (1996-05-01), Richards et al.
M. Gdula, et al, "A 36-Chip Multiprocessor Multichip Module with the General Electric High Density Interconnect Technology" IEEE, V. 91, pp. 727-730, 1991.
H. Linde, et al, "Wet Silicon Etching with Aqueous Amine Gallates" Jrl. Electrochemical Soc., V. 139, #4, pp. 1170-1174, Apr. 1992.
Marketing Materials, "High Density Multichip Interconnect--Reliability Data" Hughes Microelectronic Circuits Division, A subsidiary of GM Hughes Electornics, Newport Beach CA, 3 pages, post 1992.
R. J. Wojnarowski, et al, "Three Dimensional Hybrid Wafer Scale Integration Using the GE High Density Interconnect Technology" IEEE Conference on Wafer Scale Integration, Session 7, WSI Technology 1, pp. 309-316, 1993.
M. Despont, et al, "New Design of Micromachined Capacitive Force Sensor" Jrl. of Micromechanics & Microengineering V. 3, #4, pp. 239-242, Dec. 1993.
D. Sander, et al, "Fabrication of Metallic Microstructures by Electroplating Using Deep-Etched Silicon Molds" IEEE, Jrl. of Microelectromechanical Systems, V. 4, #2, pp. 81-86, Jun. 1995.
J. Talghader, et al, "Integration of Fluidically Self-Assembled Optoelectronic Devices Using a Silicon-Based Process" IEEE Photonics Technology Letters, vol. 7, No. 11, Nov. 1995.

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