Very dense chip package

Details Very dense chip package Very dense chip package

1998-02-04

1999-12-07

Crane, Sara

Active solid-state devices (e.g., transistors, solid-state diode

Housing or package

Outside periphery of package having specified shape or...

257684, 257724, 257618, 257506, 257510, H01L 2904

Patent

active

059988681

ABSTRACT:
An integrated circuit package or arrangement includes a carrier having a surface topography of projections or recesses for supporting individual semiconductor circuit chips having conversely matching bottom surface topographies to permit self-aligned positioning of the chips on the carrier. Top faces of neighboring chips lie substantially in planes separated by a distance of greater than 0.0 .mu.m. The neighboring chips are separated by a gap G or spacing in a range of approximately 1 .mu.m<G.ltoreq.approximately 100 .mu.m. A metallic interconnect is disposed over the top faces and the gap. Preferably, the interconnect has a gradual slope over the gap.

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