Vertically-tolerant alignment using slanted wall pedestal

Details Vertically-tolerant alignment using slanted wall pedestal Vertically-tolerant alignment using slanted wall pedestal

2001-08-14

2002-10-01

Talbott, David L. (Department: 2827)

Active solid-state devices (e.g., transistors, solid-state diode

Combined with electrical contact or lead

Chip mounted on chip

C257S685000, C257S686000, C257S723000, C257S724000, C257S730000, C257S731000

Reexamination Certificate

active

06459158

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Technical Field
The present invention generally relates to optoelectronic/photonic devices and, more particularly, to a method and apparatus for passively aligning, tacking, and bonding an optoelectronic/photonic device with a matching substrate.
2. Background
Photonic component hybridization concerns integrating optical components on a substrate or a platform with optoelectronic/photonic devices. This technology involves electrically and mechanically bonding or otherwise assembling the optoelectronic/photonic device with the optical components (e.g. waveguides, lasers, SOAs, etc.) on the substrate. A fundamental issue in photonic component hybridization is the accurate positioning of the device relative to the substrate which typically requires accuracy within one micrometer (1 &mgr;m) for proper optical coupling. One key point for such in-line hybridization is to obtain a precise alignment of the optical waveguides of the different components. Past attempts to ensure such positioning accuracy include active and passive alignment techniques but the 1 &mgr;m precision accuracy is difficult to achieve.
A widely used passive alignment technique involves the use of flip-chip solder bonding for packaging of optoelectronic components to optical waveguides. This method completely relies on the solder surface tension and the design of the wettable pads to align the waveguides to the optoelectronic components. In this bonding sequence, a chip (e.g., the device) with a plurality of solder bumps formed thereon is roughly aligned over a substrate using a pick and place machine, the temperature of the assembly is then raised above the solder melting temperature, and, upon the solder melting, surface tension appears at all interfaces which moves the chip to the lowest potential energy point which corresponds to alignment with the substrate. Once the chip is aligned, the solder is cooled.
Passive alignment techniques range in accuracy due to variations in the solder bonding process. Current dimensional accuracy requirements for photonic component hybridization is about 0.5 micrometers in the X, Y, and Z directions. As such, the uncertainty in alignment accuracy of this technique makes it unsuitable for photonic assemblies.
To eliminate the dependency of alignment accuracy on the solder bonding process, several techniques employing stops, standoffs, pedestals, registration features, fiducials, or other projections of varying shapes coupling with receiving recesses have been employed. For example, the chip to be attached has projections that are inserted into recesses on the substrate in a precisely fitted fashion, or vice a versa, as seen in FIG.
1
. In
FIG. 1
, the substrate
114
to be attached has projections
124
that are inserted into recesses
18
on the chip
12
in a precisely fitted fashion. The absolute positioning of the chip guiding structure relies on the lateral (X-direction) alignment between the optical waveguides with the assembly (fiducial) marks formed on the chip as pairs of trenches or recesses
18
. Additionally, the vertical (Z-direction) or height (h) alignment
113
relies on a proper positioning of the chip on the corresponding silicon slanted pedestal of the receiving substrate. The dimensional accuracy of the projections and the recesses is determined either by lithography or by micro-milling or micro-drilling tolerances, typically less than one micrometer. The precise lateral positioning is easier obtained due to the assembly scheme of pairs of recesses on top of corresponding pairs of pedestals or projections precisely located by the photo-lithography definition. However, in the vertical direction, there is a given uncertainty related to the fabrication of the recesses or holes and the slant of the pedestals. For typical silicon pedestals where (1,1,1) oriented sidewalls
128
are developed with an angle of 54.74°, a horizontal opening, lateral recess inaccuracy, or width tolerance &Dgr;W of +/−2 &mgr;m translates to a vertical variation or height error &Dgr;h of +/−1.48 &mgr;m. For the coupling of an active optical component, such as a laser chip, with a single mode fiber, this vertical positioning inaccuracy does not reliably minimize optical loss.
In view of the foregoing, it would be desirable to provide a method and apparatus for aligning a chip to a substrate which overcomes the drawbacks of the prior art.


REFERENCES:
patent: 5532519 (1996-07-01), Bertin et al.
patent: 5866443 (1999-02-01), Pogge et al.
patent: 6087199 (2000-07-01), Pogge et al.
patent: 6114221 (2000-09-01), Tonti et al.
patent: 6188138 (2001-02-01), Bodo et al.
Self-Aligned Optical Flip-Chip OEIC Packaging Technologies Institute of Quantum Electronics Hunziker, et al Dec. 9, 1993.
Passive Self-Aligned Low-Cost Packaging of Semiconductor Laser Arrays on Si Motherboard IEEE Photonics Tech. Letters 7/95 No. 11 Hunziker, et al.
A novel micromaching technology for multilevel structures of silicon Bao, et al State Key Laboratories of Transducer Technology Sep. 19, 1996.
Maskless etching of three-dimensional silicon structures in KOH XP000681221.
Hybrid integration onto silicon motherboards with planar silica waveguides XP00068747.

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