Vertically stacked semiconductor device

Details Vertically stacked semiconductor device Vertically stacked semiconductor device

2006-08-22

2006-08-22

Nelms, David (Department: 2818)

Active solid-state devices (e.g., transistors, solid-state diode

Housing or package

Multiple housings

C257S686000, C257S687000

Reexamination Certificate

active

07095105

ABSTRACT:
A semiconductor device including a vertical assembly of semiconductor chips interconnected on a substrate with one or more metal standoffs providing a fixed space between each supporting chip and a next successive vertically stacked chip is described. The device is fabricated by patterning islands of aluminum atop the passivation layer of each supporting chip simultaneously with processing to form bond pad caps. The fabrication process requires no additional cost, and has the advantage of providing standoffs for a plurality of chips by processing in wafer form, thereby avoiding additional assembly costs. Further, the standoffs provide improved thermal dissipation for the device and a uniform, stable bonding surface for wire bonding each of the chips to the substrate.

REFERENCES:
patent: 6016013 (2000-01-01), Baba
patent: 6232667 (2001-05-01), Hultmark et al.
patent: 6531784 (2003-03-01), Shim et al.
patent: 6650009 (2003-11-01), Her et al.
patent: 6818545 (2004-11-01), Lee et al.
patent: 2003/0127719 (2003-07-01), Chang

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