Vertically stacked bipolar dynamic random access memory

Details Vertically stacked bipolar dynamic random access memory Vertically stacked bipolar dynamic random access memory

1991-03-08

1993-11-16

Wojciechowicz, Edward

Active solid-state devices (e.g., transistors, solid-state diode

Bipolar transistor structure

Including additional component in same, non-isolated structure

257535, 257574, 257906, H01L 2702

Patent

active

052626709

ABSTRACT:
A bipolar DRAM comprises a switching transistor, a storage capacitor and a substrate. The switching transistor and the storage capacitor are vertically stacked with each other. The switching transistor is preferably an NPN bipolar transistor. The switching transistor preferably comprises P.sup.- base region, an N.sup.+ emitter region of the substrate, a N.sup.+ collector region, with a lower epitaxial layer between the N.sup.+ emitter region and P.sup.- base region, and an upper epitaxial layer between the P.sup.- base region and N.sup.+ collector region. The storage capacitor comprises a storage electrode formed on the N.sup.+ collector region, a dielectric layer and a plate electrode. The dielectric layer and the plate electrode are vertically and sequentially stacked on the storage electrode. A bit line is formed on the plate electrode, and a word line is formed on the side surface of the P.sup.+ base region.

REFERENCES:
patent: 4538244 (1985-08-01), Sugo et al.
patent: 5126814 (1992-06-01), Nakamura et al.

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