Electrical connectors – Preformed panel circuit arrangement – e.g. – pcb – icm – dip,... – With provision to conduct electricity from panel circuit to...
Patent
1998-09-08
2000-07-25
Luebke, Renee
Electrical connectors
Preformed panel circuit arrangement, e.g., pcb, icm, dip,...
With provision to conduct electricity from panel circuit to...
257685, 257686, 361790, H01R 1200
Patent
active
060930292
ABSTRACT:
An arrangement for coupling a first packaged integrated circuit to a second packaged integrated circuit comprises a first packaged integrated circuit that includes a first set of electrical interconnection elements arranged on a first surface and a second set of electrical interconnection elements arranged on a second surface which is opposite to the first side. A thermally conductive material is disposed on the second surface and the second set of electrical interconnection elements are arranged around at least a portion of the periphery of the second surface. A second packaged integrated circuit includes a third set of electrical interconnection elements arranged on a first surface of the second packaged integrated circuit. The third set of electrical interconnection elements are shaped to mechanically and electrically couple and decouple to or from the second set of electrical interconnection elements non-destructively by application of manual force.
REFERENCES:
patent: 4656605 (1987-04-01), Clayton
patent: 4684184 (1987-08-01), Grabbe et al.
patent: 4696525 (1987-09-01), Coller et al.
patent: 4727513 (1988-02-01), Clayton
patent: 4833568 (1989-05-01), Berhold
patent: 4850892 (1989-07-01), Clayton
patent: 4868712 (1989-09-01), Woodman
patent: 4953060 (1990-08-01), Lauffer et al.
patent: 5241450 (1993-08-01), Bernhardt et al.
patent: 5330359 (1994-07-01), Walker
patent: 5376825 (1994-12-01), Tukamoto et al.
patent: 5380681 (1995-01-01), Hsu
patent: 5383269 (1995-01-01), Rathmell et al.
patent: 5426563 (1995-06-01), Moresco et al.
patent: 5429511 (1995-07-01), DelPrete et al.
patent: 5445526 (1995-08-01), Hoshino et al.
patent: 5455740 (1995-10-01), Burns
patent: 5481133 (1996-01-01), Hsu
patent: 5502667 (1996-03-01), Bertin et al.
patent: 5512783 (1996-04-01), Wakefield et al.
patent: 5543660 (1996-08-01), Dombroski
patent: 5586009 (1996-12-01), Burns
patent: 5612570 (1997-03-01), Eide et al.
patent: 5619067 (1997-04-01), Sua et al.
patent: 5666272 (1997-09-01), Moore et al.
patent: 5726493 (1998-03-01), Yamashita et al.
patent: 5734555 (1998-03-01), McMahon
patent: 5821625 (1998-10-01), Yoshida et al.
patent: 5963430 (1999-10-01), Londa
Ewanich Jon
Franklin Paul
Gervasi Bill
Kwon Young
Luebke Renee
S3 Incorporated
Zarroli Michael C.
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