Active solid-state devices (e.g. – transistors – solid-state diode – Housing or package – For plural devices
Reexamination Certificate
2001-07-02
2002-05-14
Ngô, Ngân V. (Department: 2814)
Active solid-state devices (e.g., transistors, solid-state diode
Housing or package
For plural devices
C257S698000, C257S725000, C257S621000
Reexamination Certificate
active
06388320
ABSTRACT:
BACKGROUND OF THE INVENTION
Field of the Invention
In the context of new technologies, thinning semiconductor chips by grinding is of interest, e.g., to be able to mount stacks of a plurality of semiconductor chips on top of one another. For such a purpose, the semiconductor chips are thinned by grinding to such an extent that through-plating for connecting two or more layers is made possible. In addition to the possibility of handling semiconductor chip stacks having a small structural height, the through-plating of such ground-thin semiconductor chips can also be used to utilize the rear side of the semiconductor chips for circuit structures. Such use is of interest principally in the field of security and smart card ICs, because active protective structures against physical attacks can be realized (e.g., rear-side protection plate).
For such a purpose, contemporary semiconductor chips are ground to a thickness of 15-20 &mgr;m. The consequence of such grinding is that it becomes relatively difficult to further process the resulting semiconductor chips. On one hand, the semiconductor chips can “roll up”, and, on the other hand, mounting on conventional supports is relatively difficult. Furthermore, strain could occur between the layers of a stack, which, in the worst case, leads to a reduced thermal loading capacity of the configuration.
Stacks described above are already used in high-performance computers, but such use is associated with considerable costs in the handling and mounting of the chips. To avoid the above-described handling problems, that is to say, during production, temporary supports are used that are connected to the semiconductor chip only during mounting and are removed after the semiconductor chip stack has been joined together. In addition to the high costs, the complicated production method, which proceeds with a large number of method steps, is not tenable for low-cost applications.
SUMMARY OF THE INVENTION
It is accordingly an object of the invention to provide a vertically integrated semiconductor configuration that overcomes the hereinafore-mentioned disadvantages of the heretofore-known devices of this general type and that has ground-thin semiconductor chips that can be produced cost-effectively.
With the foregoing and other objects in view, there is provided, in accordance with the invention, a semiconductor configuration, including at least one semiconductor chip having a first chip side, a second chip side, and connections passing through the semiconductor chip, active structures on the first chip side and the second chip side, the connections electrically connecting the active structures to one another, a support having a first support side, a second support side, plated-through holes, and non-conducting regions running alternately with regular spacings from the first support side to the second support side, the plated-through holes spaced apart from one another to define a hole spacing distance between the holes, contact connections connecting the second chip side to the first support side, the contact connections spaced apart from one another to define a connection spacing distance between the contact connections, and the hole spacing distance being smaller than the connection spacing distance.
A semiconductor configuration having at least one semiconductor chip with a first and a second main side is proposed. The active structures are connected to one another by connections passing through the semiconductor chip and the chip is configured with one of the main sides on a first side of a support.
What is proposed, then, is to mount ground-thin semiconductor chips permanently on a cost-effective support. The mounting unites the advantages of the through-plating connection of active structures and the requisite small material thickness of the semiconductor chip with a good mechanical stability. In contrast to the prior art, the support remains in the semiconductor configuration, thereby ensuring good handleability during production. As such, it is possible to configure a plurality of chips on the first main side of the support.
In accordance with another feature of the invention, there is provided on the second main side—opposite to the first—of the support at least one further semiconductor chip having active structures on its first and second main sides, which faces the support with one of its main sides and lie opposite the semiconductor chip on the first main side of the support. The semiconductor configuration is provided in the form of a “sandwich” structure on both sides of the support. The sandwich enables a semiconductor configuration that requires only little space.
In accordance with a further feature of the invention, the support has contact connections on the first and/or the second main side, which contact connections are connected to contacts of the semiconductor chips of the active structure. The support can, thus, be used for accommodating simple passive connecting structures. In accordance with an added feature of the invention, the support has passive connecting structures. As a result, on one hand, the complexity of the active layers can be reduced and, on the other hand, a high degree of security against the separation of active structures and the support can be ensured. It is, thus, possible to connect contacts of a semiconductor chip through the passive connecting structure in the support or, alternatively, to connect contacts of different semiconductor chips through the passive connecting structure in the support. The connecting structures may be provided in one or in a plurality of planes in the support.
For such a purpose, in accordance with yet another feature of the invention, either the contact connections on the first main side of the support are connected to one another and/or the contact connections on the second main side of the support are connected to one another and/or the contact connections on the first and the second main side of the support are connected to one another through plated-through holes. The electrical connection between two semiconductor chips that are situated on the opposite main sides of the support can be realized through plated-through holes in the support. In security-relevant applications, it is advantageous if the functionality of the semiconductor configuration is ensured only when at least two semiconductor chips are electrically connected to one another. The interconnected contacts of the semiconductor chips are then advantageously respectively situated on the sides of the semiconductor chips that face the support. If the contacts between one of the semiconductor chips and the support were interrupted, the circuits realized on the semiconductor chips would no longer be functional. It is, thus, possible to prevent examination of the charge potentials produced on the lines.
In accordance with an additional feature of the invention, the support has plated-through holes and non-conducting regions running with regular spacings from the first to the second main side. The advantage of the configuration is that a universal support can be used, regardless of the position of the contacts on the active areas of the semiconductor chips, if the corresponding minimum spacings of the contacts of the semiconductor chips are complied with.
In accordance with a concomitant feature of the invention, the support is advantageously embodied as a semiconductor wafer. A semiconductor wafer serving as support can be produced cost-effectively and, moreover, has the advantage that the layer thickness can be chosen in accordance with the mechanical requirement, without influencing the technological boundary conditions of the active layer in the process. The configuration also applies, of course, to any other support, for example, made of a plastic or a ceramic. A semiconductor wafer as support additionally has the advantage that it can be connected to the semiconductor chips in a particularly simple manner. Moreover, the thermal expansion coefficients are matched to one another.
Other features that are conside
Kux Andreas
Smola Michael
Greenberg Laurence A.
Infineon - Technologies AG
Mayback Gregory L.
Ngo Ngan V.
Stemer Werner H.
LandOfFree
Vertically integrated semiconductor configuration does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Vertically integrated semiconductor configuration, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Vertically integrated semiconductor configuration will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-2825573