Vertical type MOS transistor and method of formation thereof

Details Vertical type MOS transistor and method of formation thereof Vertical type MOS transistor and method of formation thereof

1987-12-01

1989-07-04

LaRoche, Eugene R.

357 236, 357 41, 357 45, 357 51, 357 56, 357 59, H01L 2978, H01L 2702, H01L 2904

Patent

active

048455377

ABSTRACT:
A vertical MOS transistor having its channel length determined by the thickness of an insulating layer provided over a semiconductor substrate, rather than by the depth of a trench in which the transistor is formed. As a result, the characteristics of the transistor as relatively unaffected by doping and heat-treatment steps which are performed during formation. Also, the transistor may be formed so as to occupy very little surface area, making it suitable for application in high-density DRAMs. 0O048455372

REFERENCES:
patent: 3912546 (1975-10-01), Hunsperger et al.
patent: 4291327 (1981-09-01), Tsang
patent: 4466008 (1984-08-01), Beneking
patent: 4503449 (1985-03-01), David et al.
patent: 4713678 (1987-12-01), Womack et al.
patent: 4755867 (1988-07-01), Cheng
patent: 4763180 (1988-08-01), Hwang et al.

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