Vertical type MOS transistor and method of formation thereof

Details Vertical type MOS transistor and method of formation thereof Vertical type MOS transistor and method of formation thereof

1989-04-21

1991-05-21

Hearn, Brian E.

Fishing, trapping, and vermin destroying

437 41, 437 51, 437 52, 437 56, 437 89, 437203, 437233, H01L 2170

Patent

active

050175041

ABSTRACT:
A vertical MOS transistor having its channel length determined by the thickness of an insulating layer provided over a semiconductor substrate, rather than by the depth of a trench in which the transistor is formed. As a result, the characteristics of the transistor as relatively unaffected by doping and heat-treatment steps which are performed during formation. Also, the transistor may be formed so as to occupy very little surface area, making it suitable for application in high-density DRAMs.

REFERENCES:
patent: 4116720 (1978-09-01), Uinsom
patent: 4649625 (1987-03-01), Lu
patent: 4683643 (1987-08-01), Wakajima et al.
patent: 4689871 (1987-09-01), Malhi
patent: 4713678 (1987-12-01), Womack et al.
patent: 4751557 (1988-06-01), Sunami et al.
patent: 4816884 (1989-03-01), Hwano et al.
patent: 4824793 (1989-04-01), Richardson et al.

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