Vertical two-transistor flash memory

Details Vertical two-transistor flash memory Vertical two-transistor flash memory

2001-02-15

2002-05-28

Nguyen, Viet Q. (Department: 2818)

Static information storage and retrieval

Floating gate

Particular biasing

C365S185150, C365S185050, C365S185010, C365S174000, C365S182000

Reexamination Certificate

active

06396745

ABSTRACT:

BACKGROUND
1. Field of the Invention
The present invention generally relates to a vertical two-transistor memory, and in particular to a vertical two-transistor memory which can avoid word line disturb and can be programmed or erased by channel Fowler-Nordheim tunneling of electrons.
2. Description of the Prior Art
The conventional erasable programmable read only memory (EPROM) cell
100
has two polysilicon gates as shown in FIG.
1
A. The upper gate called control gain
101
is used for control and is connected to the word line. The bottom gate called floating gate
102
between the control gate
101
and the substrate
103
is isolated in the surrounding silicon dioxide. Programming of an EPROM cell
100
is achieved by applying a high voltage to both the drain
104
and the control gate
101
and grounding the source
105
. Avalanche injection , also called hot electron injection (HEI), of high energy electrons then occurs from the substrate
103
through the isolating oxide
107
under the influence of the positive applied drain voltage. The electrons must gain sufficient energy to jump the 3.2 eV energy barrier at the interface between the silicon substrate
103
and the silicon dioxide
107
. The positive voltage on the control gain then pulls the electrons through the oxide towards the floating gate
102
causing charge to be collected on the floating gate
102
. The cell is erased through internal photoemission of electrons from the floating gate
102
to the control gate
101
and the substrate
103
. This process can be achieved by exposing the EPROM to an ultra-violet (UV) light source.
An electrically erasable programmable read only memory (EEPROM) is a variation of the conventional EPROM design. EPROM tunnel oxide (ETOX) cell has been one of the most common EEPROM cells. The typical EEPROM
200
, as shown in
FIG. 2A
, consists of two transistors: one is select transistor
210
and the other is storage transistor
220
. The storage transistor
220
has an oxide region
223
between the floating gate
222
and the drain
225
where the oxide
223
is thin enough to permit Fowler-Nordheim tunneling (FN tunneling) to occur. So, the storage transistor
220
can be programmed or erased by Fowler-Nordheim tunneling of electrons through the thin oxide layer
223
between the floating gate
222
and the drain
225
of the storage transistor
220
. In the write mode the control gate
221
is grounded and the drain
225
is connected to a high voltage through the select transistor
210
. In the erase mode the control gate
221
is at the high voltage while the drain
225
is grounded. The equivalent circuit of EPROM is also shown in FIG.
1
B.
Flash memories were a direct derivative of the one-transistor cell EPROM. They resulted from innovative cell designs and improved technology that allowed the one-transistor cell EPROM to be reprogrammed electrically in the system. The structure of a typical flash memory, as shown in
FIG. 3A
, is similar to an conventional EPROM but with thinner oxide
303
under the floating gate
302
. Many of the flash memory cells that have been developed use the split gate concept in which the channel region
307
shared by the control gate
301
and the floating gate
302
, as shown in FIG.
3
A. Programming is usually by hot electron injection from the channel
307
near the drain
305
or the source
306
, and erase is usually by cold electron tunneling through the thin oxide
303
between the floating gate
302
and the drain
305
.
Two principal disturbs that can occur during programming of EPROM or flash memory are drain disturb and word line disturb.
In conventional programming of flash memory, a high voltage is applied to write data into memory cells, but is also withdrawing those electrons stored in other cells so that the data in which cells will be lost. As shown in
FIG. 3B
, in the programming of cell
12
a high voltage is applied to the bit line
1
, and at the same time the cell
11
is also affected by such high voltage so that the electrons stored in cell
11
will be gradually lost from the drain. This effect is called drain disturb. When the word line
1
is applied with a high voltage to program the cell
21
or with a negative voltage to erase the cell
21
, the data stored in cell
11
is also affected and then will be gradually lost from the gate. Such is called word line disturb.
To avoid those disturb, some control circuitry or peripherally protective circuitry may be introduced and positioned in front of the memory cells. One of prior methods for the drain disturb is using a select transistor connected to the drain of memory cell, it look just like an EEPROM. The equivalent circuit of this lateral two-transistor memory cell is shown in FIG.
2
B. And a memory array constituted by such memory cell is also shown in FIG.
2
C. In programming of the memory cell, the bit line
1
is applied with a high voltage to program the cell
11
, at the same time the control line
1
and word line
1
are also applied with adequate voltages. To avoid affecting the cell
12
, the word line
2
is no voltage, so the data stored in cell
12
can be preserved. As such, the lateral two-transistor memory cell can avoid the drain disturb. However, the memory cell provided in present invention is designed for the word line disturb.
SUMMARY
It is an object of the invention to provide a memory cell.
It is another object of the invention to provide a memory cell which can avoid the word line disturb.
It is a further object of the invention to provide a memory cell which can be programmed or erased by channel FN tunneling of electrons.
According to the foregoing objects, the present invention provides a vertical two-transistor memory cell structure which consists of a MOS transistor and an ETOX cell, wherein one of the drain and source of the MOS transistor is connected to the control gate of the ETOX cell, and the other is acted as the control gate of the vertical two-transistor memory cell and is connected to a control line. The gate of the MOS transistor is then acted as the select gate of the vertical two-transistor memory cell and is connected to a word line. The drain of the ETOX cell is connected to a bit line, and the source of the ETOX cell is grounded. We can call the MOS transistor a select transistor and the ETOX cell a storage transistor.
This vertical two-transistor memory cell can be programmed by channel FN tunneling. In the write mode the control gate and the select gate of the vertical two-transistor memory cell are applied with positively high voltage, the drain and source are grounded or floating, and the substrate is grounded, so the electrons can be pulled from the substrate through the channel and the tunnel oxide to the floating gate. Other memory cells connected to the same control line can avoid the effect of the high voltage of programming by using word lines to control the select gates, and then the data stored in those memory cell can be preserved. For this reason, we can say that the present vertical two-transistor memory cell can avoid the word line disturb. In addition, the electrons are injected through the overall channel unlike the conventional programming in which the electrons are injected from a partial region of channel near the drain. It is attributed to that the high voltage is applied to the control gate, but the drain and source are grounded.
The vertical two-transistor memory cell can also be erased by channel FN tunneling. In erase mode the select gate is applied an adequate voltage, the control gate is grounded, the source and drain are floating or applied with a voltage equal to the voltage of well, and the substrate is applied with a high voltage, so that the electrons stored in the floating gate can be withdrawn through the tunnel oxide and channel to the substrate.
In addition, the vertical two-transistor memory cell can be also programmed by conventional methods such as hot electron injection and drain FN tunneling, and can be also erased by negative gate source erase or drain FN tunneling erase

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