Active solid-state devices (e.g. – transistors – solid-state diode – Integrated circuit structure with electrically isolated... – Including high voltage or high power devices isolated from...
Reexamination Certificate
1995-02-06
2001-02-27
Loke, Steven H. (Department: 2811)
Active solid-state devices (e.g., transistors, solid-state diode
Integrated circuit structure with electrically isolated...
Including high voltage or high power devices isolated from...
C257S337000, C257S341000, C257S501000
Reexamination Certificate
active
06194773
ABSTRACT:
TECHNICAL FIELD OF THE DISCLOSURE
This invention relates in general to integrated circuits, and more particularly to a novel transistor and method of forming the same.
BACKGROUND OF THE DISCLOSURE
In power integrated circuits, there is frequently a need for several power devices to be formed on a single chip. One such application is an H-bridge driver circuit for motor control. In order to reduce the cost and increase the producibility of an integrated circuit having multiple power devices, the size of each power device must be minimized.
The size of a power device is dictated mainly by the need for a given low on-resistance (R
on
). The minimum on-resistance per unit area is normally associated with a vertical MOS device, as opposed to a lateral device. In such devices, the gate is formed on a semiconductor surface, the source is formed in a doped region of an opposite conductivity type, and the drain contact is located at the bottom of the chip. Hence, the substrate acts as the drain. When a voltage is applied to the gate, a channel is formed through the doped region, and current may flow from surface source to substrate drain.
Vertical MOS devices provide several advantages over their lateral counterparts. First, the channel width per unit area, and hence, current handling capability is higher. Further, the drain contact is at the bottom in the vertical transistors and the metal scheme required to handle high currents is simplified.
Unfortunately, in a bulk process, if more than one device is integrated on a chip using bottom drains, all drains are inherently connected together. This fairly limits the complexity of a circuit using these devices. In one proposed device, vertical transistors are set in polysilicon. This structure somewhat reduces the coupling between drains, but does not isolate the drains to a desirable degree.
Therefore, a need has arisen to provide a vertical transistor which may be isolated from other devices.
SUMMARY OF THE DISCLOSURE
In accordance with the present invention, a vertical transistor and method for forming the same is provided which substantially eliminates disadvantages associated with prior art transistors.
In the present invention, a vertical transistor comprises a semiconductor layer of a first conductivity type having a first doped region of a second conductivity type formed therein. A second doped region of the first conductivity type is formed in the first doped region. A gate overlies the first doped region such that a voltage applied to the gate creates a channel in the first doped region providing a low impedance path between the second doped region and the semiconductor layer. Isolation regions are formed through the semiconductor layer to isolate the transistor from other devices.
This aspect of the invention provides the technical advantage that several such devices may be fabricated on a single chip without having inherent connections between the drains of the devices.
REFERENCES:
patent: 4860081 (1989-08-01), Cogan
patent: 4949137 (1990-08-01), Matsuzaki et al.
patent: 5045900 (1991-09-01), Tamagawa
patent: 5072287 (1991-12-01), Nakagawa et al.
Brady III Wade James
Loke Steven H.
Swayze, Jr. W. Daniel
Telecky , Jr. Frederick J.
Texas Instruments Incorporated
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